# STP80N240K6

**STMicroelectronics** · MOSFETs · TO-220

STP80N240K6 from STMicroelectronics, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate terminal of the N-channel MOSFET; gate-source voltage is rated at ±30 V (Table 1), and the part is listed as Zener-protected. |
| 2 | D | passive | Drain terminal, also connected to the TAB; rated 800 V drain-source breakdown (V(BR)DSS) and 16 A continuous drain current at TC = 25 °C. |
| 3 | S | passive | Source terminal, the reference for VGS; the source-drain diode is rated 16 A continuous and 35 A pulsed (Table 7). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TO-220 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate-source voltage | VGS | -30 |  | 30 | V |  | 2 |
| Drain current (continuous) | ID |  |  | 16 | A | TC = 25 °C | 2 |
| Drain current (continuous) | ID |  |  | 10 | A | TC = 100 °C | 2 |
| Drain current (pulsed) | IDM |  |  | 35 | A | Pulse width limited by safe operating area | 2 |
| Total power dissipation | PTOT |  |  | 140 | W | TC = 25 °C | 2 |
| Peak diode recovery voltage slope | dv/dt(2) |  |  | 5 | V/ns | ISD ≤ 4 A; VDS (peak) = 400 V | 2 |
| Peak diode recovery current slope | di/dt(2) |  |  | 100 | A/µs | ISD ≤ 4 A; VDS (peak) = 400 V | 2 |
| MOSFET dv/dt ruggedness | dv/dt(3) |  |  | 120 | V/ns | VDS ≤ 640 V | 2 |
| Storage temperature range | Tstg | -55 |  | 150 | °C |  | 2 |
| Operating junction temperature range | TJ | -55 |  | 150 | °C |  | 2 |
| Avalanche current, repetitive or not repetitive | IAR |  |  | 3.3 | A | pulse width limited by TJ max. | 2 |
| Single pulse avalanche energy | EAS |  |  | 200 | mJ | starting TJ = 25 °C, ID = IAR, VDD = 50 V | 2 |
| Thermal resistance, junction-to-case | RthJC |  |  | 0.89 | °C/W |  | 2 |
| Thermal resistance, junction-to-ambient | RthJA |  |  | 62.5 | °C/W |  | 2 |
| Drain-source breakdown voltage | V(BR)DSS | 800 |  |  | V | VGS = 0 V, ID = 1 mA | 3 |
| Zero gate voltage drain current | IDSS |  |  | 1 | µA | VGS = 0 V, VDS = 800 V | 3 |
| Zero gate voltage drain current | IDSS |  |  | 50 | µA | VGS = 0 V, VDS = 800 V, TC = 125 °C | 3 |
| Gate body leakage current | IGSS | -1 |  | 1 | µA | VDS = 0 V, VGS = ±20 V | 3 |
| Gate threshold voltage | VGS(th) | 3 | 3.5 | 4 | V | VDS = VGS, ID = 100 µA | 3 |
| Static drain-source on-resistance | RDS(on) |  | 197 | 220 | mΩ | VGS = 10 V, ID = 7 A | 3 |
| Input capacitance | Ciss |  | 1350 |  | pF | VDS = 400 V, f = 1 MHz, VGS = 0 V | 3 |
| Output capacitance | Coss |  | 20 |  | pF | VDS = 400 V, f = 1 MHz, VGS = 0 V | 3 |
| Equivalent capacitance energy related | Co(er)(1) |  | 25 |  | pF | VDS = 0 to 640 V, VGS = 0 V | 3 |
| Equivalent capacitance time related | Co(tr)(2) |  | 139 |  | pF | VDS = 0 to 640 V, VGS = 0 V | 3 |
| Intrinsic gate resistance | RG |  | 1.8 |  | Ω | f = 1 MHz, ID = 0 A | 3 |
| Total gate charge | Qg |  | 25.9 |  | nC | VDD = 640 V, ID = 7 A, VGS = 0 to 10 V | 3 |
| Gate-source charge | Qgs |  | 6.9 |  | nC | VDD = 640 V, ID = 7 A, VGS = 0 to 10 V | 3 |
| Gate-drain charge | Qgd |  | 8.4 |  | nC | VDD = 640 V, ID = 7 A, VGS = 0 to 10 V | 3 |
| Turn-on delay time | td(on) |  | 16 |  | ns | VDD = 400 V, ID = 7 A, RG = 4.7 Ω, VGS = 10 V | 3 |
| Rise time | tr |  | 5.3 |  | ns | VDD = 400 V, ID = 7 A, RG = 4.7 Ω, VGS = 10 V | 3 |
| Turn-off delay time | td(off) |  | 47.8 |  | ns | VDD = 400 V, ID = 7 A, RG = 4.7 Ω, VGS = 10 V | 3 |
| Fall time | tf |  | 12 |  | ns | VDD = 400 V, ID = 7 A, RG = 4.7 Ω, VGS = 10 V | 3 |
| Source-drain current | ISD |  |  | 16 | A |  | 4 |
| Source-drain current (pulsed) | ISDM(1) |  |  | 35 | A |  | 4 |
| Forward on voltage | VSD(2) |  |  | 1.5 | V | ISD = 14 A, VGS = 0 V | 4 |
| Reverse recovery time | trr |  |  | 335 | ns | ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V | 4 |
| Reverse recovery charge | Qrr |  |  | 5.4 | µC | ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V | 4 |
| Reverse recovery current | IRRM |  |  | 27.5 | A | ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V | 4 |
| Reverse recovery time | trr |  |  | 430 | ns | ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C | 4 |
| Reverse recovery charge | Qrr |  |  | 7.4 | µC | ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C | 4 |
| Reverse recovery current | IRRM |  |  | 28 | A | ISD = 14 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C | 4 |

## CAD (KiCad official)

- Symbol: `STP80N240K6`
- Footprint: `Package_TO_SOT_THT:TO-220-3_Vertical`
- 3D model: TO-220 (KiCad packages3D, STEP)
- 3D model files: `stp80n240k6-etched.step` / `stp80n240k6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stp80n240k6.step` / `stp80n240k6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stp80n240k6.pdf) (13 pp, sha256 `9f1cfb42fd8c48bb`, retrieved 2026-10-10, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stp80n240k6-datasheet.pdf)