# STP100NF04

**STMicroelectronics** · MOSFETs · TO-220

STP100NF04 from STMicroelectronics, in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate terminal; gate-source voltage VGS is limited to ±20 V. |
| 2 | D | passive | Drain terminal, electrically connected to the TAB; drain-source voltage VDS is limited to 40 V and continuous drain current is 120 A at TC = 25 °C (current limited by package). |
| 3 | S | passive | Source terminal; source-drain current ISD is rated at 120 A continuous and 480 A pulsed. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TO-220 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source breakdown voltage | V(BR)DSS | 40 |  |  | V | ID = 250 µA, VGS = 0 V | 4 |
| Zero gate voltage drain current | IDSS |  |  | 1 | µA | VDS = 40 V, VGS = 0 V | 4 |
| Zero gate voltage drain current (TC = 125°C) | IDSS |  |  | 10 | µA | VDS = 40 V, VGS = 0 V, TC = 125°C | 4 |
| Gate body leakage current | IGSS | -100 |  | 100 | nA | VGS = ±20 V, VDS = 0 V | 4 |
| Gate threshold voltage | VGS(th) | 2 |  | 4 | V | VDS = VGS, ID = 250 µA | 4 |
| Static drain-source on-resistance | RDS(on) |  | 4.3 | 4.6 | mΩ | VGS = 10 V, ID = 50 A | 4 |
| Source-drain current | ISD |  |  | 120 | A |  | 5 |
| Source-drain current (pulsed) | ISDM |  |  | 480 | A | Pulse width limited by safe operating area | 5 |
| Input capacitance | Ciss |  | 5100 |  | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 4 |
| Output capacitance | Coss |  | 1300 |  | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 4 |
| Reverse transfer capacitance | Crss |  | 160 |  | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 4 |
| Total gate charge | Qg |  | 110 | 150 | nC | VDD = 32 V, ID = 120 A, VGS = 10 V | 4 |
| Gate-source charge | Qgs |  | 35 |  | nC | VDD = 32 V, ID = 120 A, VGS = 10 V | 4 |
| Gate-drain charge | Qgd |  | 70 |  | nC | VDD = 32 V, ID = 120 A, VGS = 10 V | 4 |
| Turn-on delay time | td(on) |  | 35 |  | ns | VDD = 20 V, ID = 60 A, RG = 4.7 Ω, VGS = 10 V | 4 |
| Rise time | tr |  | 220 |  | ns | VDD = 20 V, ID = 60 A, RG = 4.7 Ω, VGS = 10 V | 4 |
| Turn-off delay time | td(off) |  | 80 |  | ns | VDD = 20 V, ID = 60 A, RG = 4.7 Ω, VGS = 10 V | 4 |
| Fall time | tf |  | 50 |  | ns | VDD = 20 V, ID = 60 A, RG = 4.7 Ω, VGS = 10 V | 4 |
| Forward on voltage | VSD |  | 1.3 |  | V | ISD = 120 A, VGS = 0 V | 5 |
| Reverse recovery time | tr |  | 75 |  | ns | ISD = 120 A, VDD = 20 V, di/dt = 100 A/µs, Tj = 150 °C | 5 |
| Reverse recovery charge | td(off) |  | 185 |  | nC | ISD = 120 A, VDD = 20 V, di/dt = 100 A/µs, Tj = 150 °C | 5 |
| Reverse recovery current | tf |  | 5 |  | A | ISD = 120 A, VDD = 20 V, di/dt = 100 A/µs, Tj = 150 °C | 5 |
| Drain-source voltage | VDS |  |  | 40 | V |  | 3 |
| Gate-source voltage | VGS | -20 |  | 20 | V |  | 3 |
| Drain current (continuous) | ID |  |  | 120 | A | TC = 25°C; current limited by package | 3 |
| Drain current (pulsed) | IDM |  |  | 480 | A | Pulse width limited by safe operating area | 3 |
| Total dissipation | PTOT |  |  | 300 | W | TC = 25°C | 3 |
| Peak diode recovery voltage slope | dv/dt |  |  | 6 | V/ns | ISD ≤ 120 A, di/dt ≤ 300 A/µs, VDD = V(BR)DSS, Tj ≤ TJMAX | 3 |
| Single pulse avalanche energy | EAS |  |  | 1.2 | J | Starting Tj = 25 °C, ID = 60 A, VDD = 30 V | 3 |
| Operating junction temperature range | Tj | -55 |  | 175 | °C |  | 3 |
| Thermal resistance junction-case | Rthj-case |  | 0.5 |  | °C/W |  | 3 |
| Thermal resistance junction-pcb | Rthj-pcb |  | 35 |  | °C/W | Mounted on a 1-inch² FR-4 board, 2oz Cu | 3 |
| Thermal resistance junction-ambient | Rthj-amb |  | 62.5 |  | °C/W |  | 3 |

## CAD (KiCad official)

- Symbol: `STP100NF04`
- Footprint: `Package_TO_SOT_THT:TO-220-3_Vertical`
- 3D model: TO-220 (KiCad packages3D, STEP)
- 3D model files: `stp100nf04-etched.step` / `stp100nf04-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stp100nf04.step` / `stp100nf04.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603058587426177024) (20 pp, sha256 `86cfaab86fe21696`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stp100nf04-datasheet.pdf)