# STN4260

**STANSON Tech** · MOSFETs · SOP-8

STN4260 from STANSON Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET, tied internally to pins 2 and 3. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, tied internally to pins 1 and 3. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, tied internally to pins 1 and 2. |
| 4 | G | input | Gate terminal; VGS rated ±20 V with threshold 1.0 to 2.5 V at ID=250uA. |
| 5 | D | passive | Drain terminal, tied internally to pins 6, 7 and 8; VDSS 60 V. |
| 6 | D | passive | Drain terminal, tied internally to pins 5, 7 and 8; VDSS 60 V. |
| 7 | D | passive | Drain terminal, tied internally to pins 5, 6 and 8; VDSS 60 V. |
| 8 | D | passive | Drain terminal, tied internally to pins 5, 6 and 7; VDSS 60 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STANSON Tech |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS |  |  | 60 | V | Ta = 25℃ unless otherwise noted | 2 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 2 |
| Continuous Drain Current | ID |  |  | 20 | A | TJ=150℃, TA=25℃ | 2 |
| Continuous Drain Current | ID |  |  | 14 | A | TJ=150℃, TA=70℃ | 2 |
| Pulsed Drain Current | IDM |  |  | 110 | A |  | 2 |
| Continuous Source Current (Diode Conduction) | IS |  |  | 4.5 | A |  | 2 |
| Power Dissipation | PD |  |  | 3.1 | W | TA=25℃ | 2 |
| Power Dissipation | PD |  |  | 2 | W | TA=70℃ | 2 |
| Operation Junction Temperature | TJ |  |  | 150 | ℃ |  | 2 |
| Storage Temperature Range | TSTG | -55 |  | 150 | ℃ |  | 2 |
| Thermal Resistance-Junction to Ambient | RθJA |  |  | 70 | ℃/W |  | 2 |
| Drain-Source Breakdown Voltage | V(BR)DSS | 60 |  |  | V | VGS=0V, ID=250uA | 3 |
| Gate Threshold Voltage | VGS(th) | 1 |  | 2.5 | V | VDS=VGS, ID=250uA | 3 |
| Gate Leakage Current | IGSS | -100 |  | 100 | nA | VDS=0V, VGS=±20V | 3 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 1 | uA | VDS=60V, VGS=0V | 3 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 5 | uA | VDS=60V, VGS=0V, TJ=25℃ | 3 |
| Drain-source On-Resistance | RDS(on) |  | 11.5 | 13 | mΩ | VGS=10V, ID=10A | 3 |
| Drain-source On-Resistance | RDS(on) |  | 12.5 | 14 | mΩ | VGS=4.5V, ID=8A | 3 |
| Diode Forward Voltage | VSD |  | 0.8 | 1 | V | IS=1A, VGS=0V | 3 |
| Total Gate Charge | Qg |  | 40 | 58 | nC | VDS=30V, VGS=10V, ID≡10A | 3 |
| Gate-Source Charge | Qgs |  | 6 | 9 | nC | VDS=30V, VGS=10V, ID≡10A | 3 |
| Gate-Drain Charge | Qgd |  | 8.8 | 14 | nC | VDS=30V, VGS=10V, ID≡10A | 3 |
| Turn-On Delay Time | td(on) |  | 9.5 | 18 | nS | VDD=15V, VGS=10V, RG=6Ω, ID=1A | 3 |
| Turn-On Rise Time | tr |  | 28 | 54 | nS | VDD=15V, VGS=10V, RG=6Ω, ID=1A | 3 |
| Turn-Off Delay Time | td(off) |  | 45.3 | 86 | nS | VDD=15V, VGS=10V, RG=6Ω, ID=1A | 3 |
| Turn-Off Fall Time | tf |  | 80 | 120 | nS | VDD=15V, VGS=10V, RG=6Ω, ID=1A | 3 |
| Forward Transconductance | gfs |  | 11.7 |  | S | VDS=10V, ID=6A | 3 |
| Input Capacitance | Ciss |  | 2100 |  | pF | VDS=25V, VGS=0V, F=1MHz | 3 |
| Output Capacitance | Coss |  | 165 |  | pF | VDS=25V, VGS=0V, F=1MHz | 3 |
| Reverse Transfer Capacitance | Crss |  | 80 |  | pF | VDS=25V, VGS=0V, F=1MHz | 3 |

## CAD (KiCad official)

- Symbol: `STN4260`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `stn4260-etched.step` / `stn4260-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stn4260.step` / `stn4260.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STANSON Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907494067851264) (6 pp, sha256 `ff2f37f602c1abc5`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stn4260-datasheet.pdf)