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STM8S105K4T3CTR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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STM8S105K4T3CTR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM8S105K4T3CTR from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Reset input/output pin (I/O, no alternate function listed).
2 PA1/OSCIN bidirectional Port A1 I/O (slow, up to 2 MHz, O1) whose alternate function is resonator/crystal input OSCIN, or external clock input when OPT4 EXTCLK=1.
3 PA2/OSCOUT bidirectional Port A2 I/O (slow, up to 2 MHz, O1) whose alternate function is resonator/crystal output OSCOUT.
4 VSS power_in Digital ground.
5 VCAP passive Connection for the 1.8 V regulator external capacitor.
6 VDD power_in Digital power supply; device operating voltage is 2.95 to 5.5 V.
7 VDDIO power_in I/O power supply (listed as VDDIO_1 in the table).
8 PF4/AIN12 bidirectional Port F4 I/O (slow, O1) with analog input 12; pulled up during reset, floating input after reset release, and AIN12 is not selectable in ADC scan mode or with analog watchdog.
9 VDDA power_in Analog power supply.
10 VSSA power_in Analog ground.
11 PB5/AIN5 bidirectional Port B5 I/O (slow, O1, external interrupt) with analog input 5; I2C_SDA after remap with option bit AFR6.
12 PB4/AIN4 bidirectional Port B4 I/O (slow, O1, external interrupt) with analog input 4; I2C_SCL after remap with option bit AFR6.
13 PB3/AIN3 bidirectional Port B3 I/O (slow, O1, external interrupt) with analog input 3; TIM1_ETR after remap with option bit AFR5.
14 PB2/AIN2 bidirectional Port B2 I/O (slow, O1, external interrupt) with analog input 2; TIM1_CH3N after remap with option bit AFR5.
15 PB1/AIN1 bidirectional Port B1 I/O (slow, O1, external interrupt) with analog input 1; TIM1_CH2N after remap with option bit AFR5.
16 PB0/AIN0 bidirectional Port B0 I/O (slow, O1, external interrupt) with analog input 0; TIM1_CH1N after remap with option bit AFR5.
17 PE5/SPI_NSS bidirectional Port E5 I/O (slow, O1, external interrupt) used as SPI master/slave select.
18 PC1/TIM1_CH1/UART2_CK bidirectional Port C1 high-sink I/O (O3, external interrupt) used as Timer 1 channel 1 or UART2 synchronous clock.
19 PC2/TIM1_CH2 bidirectional Port C2 high-sink I/O (O3, external interrupt) used as Timer 1 channel 2.
20 PC3/TIM1_CH3 bidirectional Port C3 high-sink I/O (O3, external interrupt) used as Timer 1 channel 3.
21 PC4/TIM1_CH4 bidirectional Port C4 high-sink I/O (O3, external interrupt) used as Timer 1 channel 4.
22 PC5/SPI_SCK bidirectional Port C5 high-sink I/O (O3) used as SPI clock.
23 PC6/SPI_MOSI bidirectional Port C6 high-sink I/O (O3, external interrupt) used as SPI master out/slave in.
24 PC7/SPI_MISO bidirectional Port C7 high-sink I/O (O3, external interrupt) used as SPI master in/slave out.
25 PD0/TIM3_CH2 bidirectional Port D0 high-sink I/O (O3, external interrupt) used as Timer 3 channel 2; TIM1_BKIN with AFR3 or CLK_CCO with AFR2 after remap.
26 PD1/SWIM bidirectional Port D1 high-sink I/O (O4, external interrupt) used as SWIM data interface; input pull-up during reset and after internal reset release.
27 PD2/TIM3_CH1 bidirectional Port D2 high-sink I/O (O3, external interrupt) used as Timer 3 channel 1; TIM2_CH3 after remap with option bit AFR1.
28 PD3/TIM2_CH2 bidirectional Port D3 high-sink I/O (O3, external interrupt) used as Timer 2 channel 2; ADC_ETR after remap with option bit AFR0.
29 PD4/TIM2_CH1 bidirectional Port D4 high-sink I/O (O3, external interrupt) used as Timer 2 channel 1; BEEP output after remap with option bit AFR7.
30 PD5/UART2_TX bidirectional Port D5 I/O (slow, O1, external interrupt) used as UART2 data transmit.
31 PD6/UART2_RX bidirectional Port D6 I/O (slow, O1, external interrupt) used as UART2 data receive.
32 PD7/TLI bidirectional Port D7 I/O (slow, O1, external interrupt) used as top level interrupt; TIM1_CH4 after remap with option bit AFR4.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

CAD (KiCad official)

  • Symbol: STM8S105K4T3CTR
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm8s105k4t3ctr-etched.step / stm8s105k4t3ctr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s105k4t3ctr.step / stm8s105k4t3ctr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (121 pp, sha256 b1007bc27bb78327, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF