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STM8S103K3T3C

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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STM8S103K3T3C

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM8S103K3T3C from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Reset pin (I/O, weak pull-up) used for the device reset; its characteristics are given in the NRST pin characteristics table (Table 42).
2 PA1/OSCIN bidirectional Port A1 is also the resonator/crystal input OSCIN, and in Halt/Active-halt it is forced to input weak pull-up and cannot wake the device, so it should be used only as an input if Halt/Active-halt is used.
3 PA2/OSCOUT bidirectional Port A2 is also the resonator/crystal output OSCOUT (slow O1 output speed, with weak pull-up and push-pull/open-drain options).
4 VSS power_in Digital ground.
5 VCAP passive Connection for the 1.8 V regulator capacitor, whose external VCAP specification is given in Section 10.3.1.
6 VDD power_in Digital power supply, specified for 2.95 to 5.5 V operation.
7 PA3/TIM2_CH3 [SPI_NSS] bidirectional Port A3 with default Timer 2 channel 3 function, high sink capable, and SPI master/slave select available only when remapped via AFR1.
8 PF4 bidirectional Port F4 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output.
9 PB7 bidirectional Port B7 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output.
10 PB6 bidirectional Port B6 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output.
11 PB5/I2C_SDA bidirectional Port B5 with I2C data line as a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD not implemented).
12 PB4/I2C_SCL bidirectional Port B4 with I2C clock line as a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD not implemented).
13 PB3/AIN3/TIM1_ETR bidirectional Port B3 with analog input 3 and Timer 1 external trigger, high sink capable with programmable speed (O3).
14 PB2/AIN2/TIM1_CH3N bidirectional Port B2 with analog input 2 and Timer 1 inverted channel 3, high sink capable with programmable speed (O3).
15 PB1/AIN1/TIM1_CH2N bidirectional Port B1 with analog input 1 and Timer 1 inverted channel 2, high sink capable with programmable speed (O3).
16 PB0/AIN0/TIM1_CH1N bidirectional Port B0 with analog input 0 and Timer 1 inverted channel 1, high sink capable with programmable speed (O3).
17 PE5/SPI_NSS bidirectional Port E5 with SPI master/slave select, high sink capable with programmable speed (O3).
18 PC1/TIM1_CH1/UART1_CK bidirectional Port C1 with Timer 1 channel 1 and UART1 clock, high sink capable with programmable speed (O3).
19 PC2/TIM1_CH2 bidirectional Port C2 with Timer 1 channel 2, high sink capable with programmable speed (O3).
20 PC3/TIM1_CH3 bidirectional Port C3 with Timer 1 channel 3, high sink capable with programmable speed (O3).
21 PC4/TIM1_CH4/CLK_CCO bidirectional Port C4 with Timer 1 channel 4 or configurable clock output, high sink capable with programmable speed (O3).
22 PC5/SPI_SCK bidirectional Port C5 with SPI clock, high sink capable with programmable speed (O3).
23 PC6/SPI_MOSI bidirectional Port C6 with SPI master out / slave in, high sink capable with programmable speed (O3).
24 PC7/SPI_MISO bidirectional Port C7 with SPI master in / slave out, high sink capable with programmable speed (O3).
25 PD0/TIM1_BKIN [CLK_CCO] bidirectional Port D0 with Timer 1 break input, and configurable clock output available when remapped via AFR5; high sink capable.
26 PD1/SWIM bidirectional SWIM single-wire data interface, with input pull-up during reset phase and after internal reset release; high sink capable with fast/slow programmable speed (O4).
27 PD2 [TIM2_CH3] bidirectional Port D2 general-purpose I/O, high sink capable; Timer 2 channel 3 is available only when remapped via AFR1.
28 PD3/TIM2_CH2/ADC_ETR bidirectional Port D3 with Timer 2 channel 2 and ADC external trigger, high sink capable with programmable speed (O3).
29 PD4/BEEP/TIM2_CH1 bidirectional Port D4 with Timer 2 channel 1 and BEEP output, high sink capable with programmable speed (O3).
30 PD5/UART1_TX bidirectional Port D5 with UART1 data transmit, high sink capable with programmable speed (O3).
31 PD6/UART1_RX bidirectional Port D6 with UART1 data receive, high sink capable with programmable speed (O3).
32 PD7/TLI [TIM1_CH4] bidirectional Port D7 with top level interrupt (TLI) input; Timer 1 channel 4 is available only when remapped via AFR6; high sink capable.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

CAD (KiCad official)

  • Symbol: STM8S103K3T3C
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm8s103k3t3c-etched.step / stm8s103k3t3c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s103k3t3c.step / stm8s103k3t3c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (121 pp, sha256 ac23789ac0a2f408, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF