component
STM8S103K3T3C
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+68@@ -0,0 +1,68 @@+# STM8S103K3T3C++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)++STM8S103K3T3C from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NRST | bidirectional | Reset pin (I/O, weak pull-up) used for the device reset; its characteristics are given in the NRST pin characteristics table (Table 42). |+| 2 | PA1/OSCIN | bidirectional | Port A1 is also the resonator/crystal input OSCIN, and in Halt/Active-halt it is forced to input weak pull-up and cannot wake the device, so it should be used only as an input if Halt/Active-halt is used. |+| 3 | PA2/OSCOUT | bidirectional | Port A2 is also the resonator/crystal output OSCOUT (slow O1 output speed, with weak pull-up and push-pull/open-drain options). |+| 4 | VSS | power_in | Digital ground. |+| 5 | VCAP | passive | Connection for the 1.8 V regulator capacitor, whose external VCAP specification is given in Section 10.3.1. |+| 6 | VDD | power_in | Digital power supply, specified for 2.95 to 5.5 V operation. |+| 7 | PA3/TIM2_CH3 [SPI_NSS] | bidirectional | Port A3 with default Timer 2 channel 3 function, high sink capable, and SPI master/slave select available only when remapped via AFR1. |+| 8 | PF4 | bidirectional | Port F4 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output. |+| 9 | PB7 | bidirectional | Port B7 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output. |+| 10 | PB6 | bidirectional | Port B6 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output. |+| 11 | PB5/I2C_SDA | bidirectional | Port B5 with I2C data line as a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD not implemented). |+| 12 | PB4/I2C_SCL | bidirectional | Port B4 with I2C clock line as a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD not implemented). |+| 13 | PB3/AIN3/TIM1_ETR | bidirectional | Port B3 with analog input 3 and Timer 1 external trigger, high sink capable with programmable speed (O3). |+| 14 | PB2/AIN2/TIM1_CH3N | bidirectional | Port B2 with analog input 2 and Timer 1 inverted channel 3, high sink capable with programmable speed (O3). |+| 15 | PB1/AIN1/TIM1_CH2N | bidirectional | Port B1 with analog input 1 and Timer 1 inverted channel 2, high sink capable with programmable speed (O3). |+| 16 | PB0/AIN0/TIM1_CH1N | bidirectional | Port B0 with analog input 0 and Timer 1 inverted channel 1, high sink capable with programmable speed (O3). |+| 17 | PE5/SPI_NSS | bidirectional | Port E5 with SPI master/slave select, high sink capable with programmable speed (O3). |+| 18 | PC1/TIM1_CH1/UART1_CK | bidirectional | Port C1 with Timer 1 channel 1 and UART1 clock, high sink capable with programmable speed (O3). |+| 19 | PC2/TIM1_CH2 | bidirectional | Port C2 with Timer 1 channel 2, high sink capable with programmable speed (O3). |+| 20 | PC3/TIM1_CH3 | bidirectional | Port C3 with Timer 1 channel 3, high sink capable with programmable speed (O3). |+| 21 | PC4/TIM1_CH4/CLK_CCO | bidirectional | Port C4 with Timer 1 channel 4 or configurable clock output, high sink capable with programmable speed (O3). |+| 22 | PC5/SPI_SCK | bidirectional | Port C5 with SPI clock, high sink capable with programmable speed (O3). |+| 23 | PC6/SPI_MOSI | bidirectional | Port C6 with SPI master out / slave in, high sink capable with programmable speed (O3). |+| 24 | PC7/SPI_MISO | bidirectional | Port C7 with SPI master in / slave out, high sink capable with programmable speed (O3). |+| 25 | PD0/TIM1_BKIN [CLK_CCO] | bidirectional | Port D0 with Timer 1 break input, and configurable clock output available when remapped via AFR5; high sink capable. |+| 26 | PD1/SWIM | bidirectional | SWIM single-wire data interface, with input pull-up during reset phase and after internal reset release; high sink capable with fast/slow programmable speed (O4). |+| 27 | PD2 [TIM2_CH3] | bidirectional | Port D2 general-purpose I/O, high sink capable; Timer 2 channel 3 is available only when remapped via AFR1. |+| 28 | PD3/TIM2_CH2/ADC_ETR | bidirectional | Port D3 with Timer 2 channel 2 and ADC external trigger, high sink capable with programmable speed (O3). |+| 29 | PD4/BEEP/TIM2_CH1 | bidirectional | Port D4 with Timer 2 channel 1 and BEEP output, high sink capable with programmable speed (O3). |+| 30 | PD5/UART1_TX | bidirectional | Port D5 with UART1 data transmit, high sink capable with programmable speed (O3). |+| 31 | PD6/UART1_RX | bidirectional | Port D6 with UART1 data receive, high sink capable with programmable speed (O3). |+| 32 | PD7/TLI [TIM1_CH4] | bidirectional | Port D7 with top level interrupt (TLI) input; Timer 1 channel 4 is available only when remapped via AFR6; high sink capable. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-32(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 32 |++## CAD (KiCad official)++- Symbol: `STM8S103K3T3C`+- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`+- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)+- 3D model files: `stm8s103k3t3c-etched.step` / `stm8s103k3t3c-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8s103k3t3c.step` / `stm8s103k3t3c.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922134751531008) (121 pp, sha256 `ac23789ac0a2f408`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm8s103k3t3c-datasheet.pdf)
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its characteristics are given in the NRST pin characteristics table (Table 42)."+ },+ {+ "number": "2",+ "name": "PA1/OSCIN",+ "type": "bidirectional",+ "description": "Port A1 is also the resonator/crystal input OSCIN, and in Halt/Active-halt it is forced to input weak pull-up and cannot wake the device, so it should be used only as an input if Halt/Active-halt is used."+ },+ {+ "number": "3",+ "name": "PA2/OSCOUT",+ "type": "bidirectional",+ "description": "Port A2 is also the resonator/crystal output OSCOUT (slow O1 output speed, with weak pull-up and push-pull/open-drain options)."+ },+ {+ "number": "4",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "5",+ "name": "VCAP",+ "type": "passive",+ "description": "Connection for the 1.8 V regulator capacitor, whose external VCAP specification is given in Section 10.3.1."+ },+ {+ "number": "6",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital power supply, specified for 2.95 to 5.5 V operation."+ },+ {+ "number": "7",+ "name": "PA3/TIM2_CH3 [SPI_NSS]",+ "type": "bidirectional",+ "description": "Port A3 with default Timer 2 channel 3 function, high sink capable, and SPI master/slave select available only when remapped via AFR1."+ },+ {+ "number": "8",+ "name": "PF4",+ "type": "bidirectional",+ "description": "Port F4 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output."+ },+ {+ "number": "9",+ "name": "PB7",+ "type": "bidirectional",+ "description": "Port B7 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output."+ },+ {+ "number": "10",+ "name": "PB6",+ "type": "bidirectional",+ "description": "Port B6 general-purpose I/O with slow output speed (O1), floating/weak pull-up input options and push-pull output."+ },+ {+ "number": "11",+ "name": "PB5/I2C_SDA",+ "type": "bidirectional",+ "description": "Port B5 with I2C data line as a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD not implemented)."+ },+ {+ "number": "12",+ "name": "PB4/I2C_SCL",+ "type": "bidirectional",+ "description": "Port B4 with I2C clock line as a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD not implemented)."+ },+ {+ "number": "13",+ "name": "PB3/AIN3/TIM1_ETR",+ "type": "bidirectional",+ "description": "Port B3 with analog input 3 and Timer 1 external trigger, high sink capable with programmable speed (O3)."+ },+ {+ "number": "14",+ "name": "PB2/AIN2/TIM1_CH3N",+ "type": "bidirectional",+ "description": "Port B2 with analog input 2 and Timer 1 inverted channel 3, high sink capable with programmable speed (O3)."+ },+ {+ "number": "15",+ "name": "PB1/AIN1/TIM1_CH2N",+ "type": "bidirectional",+ "description": "Port B1 with analog input 1 and Timer 1 inverted channel 2, high sink capable with programmable speed (O3)."+ },+ {+ "number": "16",+ "name": "PB0/AIN0/TIM1_CH1N",+ "type": "bidirectional",+ "description": "Port B0 with analog input 0 and Timer 1 inverted channel 1, high sink capable with programmable speed (O3)."+ },+ {+ "number": "17",+ "name": "PE5/SPI_NSS",+ "type": "bidirectional",+ "description": "Port E5 with SPI master/slave select, high sink capable with programmable speed (O3)."+ },+ {+ "number": "18",+ "name": "PC1/TIM1_CH1/UART1_CK",+ "type": "bidirectional",+ "description": "Port C1 with Timer 1 channel 1 and UART1 clock, high sink capable with programmable speed (O3)."+ },+ {+ "number": "19",+ "name": "PC2/TIM1_CH2",+ "type": "bidirectional",+ "description": "Port C2 with Timer 1 channel 2, high sink capable with programmable speed (O3)."+ },+ {+ "number": "20",+ "name": "PC3/TIM1_CH3",+ "type": "bidirectional",+ "description": "Port C3 with Timer 1 channel 3, high sink capable with programmable speed (O3)."+ },+ {+ "number": "21",+ "name": "PC4/TIM1_CH4/CLK_CCO",+ "type": "bidirectional",+ "description": "Port C4 with Timer 1 channel 4 or configurable clock output, high sink capable with programmable speed (O3)."+ },+ {+ "number": "22",+ "name": "PC5/SPI_SCK",+ "type": "bidirectional",+ "description": "Port C5 with SPI clock, high sink capable with programmable speed (O3)."+ },+ {+ "number": "23",+ "name": "PC6/SPI_MOSI",+ "type": "bidirectional",+ "description": "Port C6 with SPI master out / slave in, high sink capable with programmable speed (O3)."+ },+ {+ "number": "24",+ "name": "PC7/SPI_MISO",+ "type": "bidirectional",+ "description": "Port C7 with SPI master in / slave out, high sink capable with programmable speed (O3)."+ },+ {+ "number": "25",+ "name": "PD0/TIM1_BKIN [CLK_CCO]",+ "type": "bidirectional",+ "description": "Port D0 with Timer 1 break input, and configurable clock output available when remapped via AFR5; high sink capable."+ },+ {+ "number": "26",+ "name": "PD1/SWIM",+ "type": "bidirectional",+ "description": "SWIM single-wire data interface, with input pull-up during reset phase and after internal reset release; high sink capable with fast/slow programmable speed (O4)."+ },+ {+ "number": "27",+ "name": "PD2 [TIM2_CH3]",+ "type": "bidirectional",+ "description": "Port D2 general-purpose I/O, high sink capable; Timer 2 channel 3 is available only when remapped via AFR1."+ },+ {+ "number": "28",+ "name": "PD3/TIM2_CH2/ADC_ETR",+ "type": "bidirectional",+ "description": "Port D3 with Timer 2 channel 2 and ADC external trigger, high sink capable with programmable speed (O3)."+ },+ {+ "number": "29",+ "name": "PD4/BEEP/TIM2_CH1",+ "type": "bidirectional",+ "description": "Port D4 with Timer 2 channel 1 and BEEP output, high sink capable with programmable speed (O3)."+ },+ {+ "number": "30",+ "name": "PD5/UART1_TX",+ "type": "bidirectional",+ "description": "Port D5 with UART1 data transmit, high sink capable with programmable speed (O3)."+ },+ {+ "number": "31",+ "name": "PD6/UART1_RX",+ "type": "bidirectional",+ "description": "Port D6 with UART1 data receive, high sink capable with programmable speed (O3)."+ },+ {+ "number": "32",+ "name": "PD7/TLI [TIM1_CH4]",+ "type": "bidirectional",+ "description": "Port D7 with top level interrupt (TLI) input; Timer 1 channel 4 is available only when remapped via AFR6; high sink capable."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Datasheet classifies VCAP only as power type 'S' with the note '1.8 V regulator capacitor'; it does ; Datasheet lists NRST as type I/O with weak pull-up and no explicit input/output direction limits in ; Port pins are typed bidirectional (datasheet type 'I/O'). Alternate-function names in square bracket"+ ],+ "pages_sent": 57,+ "cost_usd": 0.2266,+ "at": "2026-10-07T21:48:06"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922134751531008",+ "pages": 121,+ "sha256": "ac23789ac0a2f408",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 32,+ "described": 32,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "stm8s103k3t3c.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "be0e412f1c66fee70039b0e109e0cc7c823161dda97593718afa97569bc61ce3",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "stm8s103k3t3c-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "26f935b2a60631d04caadf7d50e3f091489139a4a6b1e8626dcb167671b177b3",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}