component
STM6600AS24DM6F
Public Made by Adomby adom
STMicroelectronics Supervisor And Reset ICs, TDFN-12(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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|---|---|
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| stm6600as24dm6f-etched.step | 19h ago |
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STM6600AS24DM6F
STMicroelectronics · Supervisor And Reset ICs · TDFN-12(2x3)
STM6600AS24DM6F from STMicroelectronics, in a TDFN-12(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Power supply input that is monitored during startup and normal operation and should be decoupled to ground with a 0.1 µF capacitor placed as close to the device as possible. |
| 2 | SR | input | Smart Reset button input with ±8 kV HBM ESD protection that must be held together with PB for tSRD to recognize a long push and must not be grounded permanently. |
| 3 | VREF | power_out | Precise 1.5 V voltage reference with 1% accuracy that requires a mandatory 1 µF capacitor even when unused and is disabled in standby mode. |
| 4 | PSHOLD | input | Power supply hold input compared to an accurate reference, where a high level during power-up confirms start-up and a low level during normal operation deasserts the enable output. |
| 5 | CSRD | passive | Adjustable Smart Reset delay input where a capacitor to ground sets the additional delay tSRD, and the pin is left open if no capacitor is used. |
| 6 | PB | input | Power-on push-button input with ±8 kV HBM ESD protection that must switch to GND, has an internal 100 kΩ pull-up, and requires VCC above VTH+ for the whole tDEBOUNCE period to power up. |
| 7 | VCCLO | output | High-threshold detection output that is active low and open drain by default, requires a pull-up resistor (10 kΩ is sufficient in most applications), and is low when VCC is below VTH+. |
| 8 | PBOUT | output | Status output of the PB input that is active low and open drain by default, requires a pull-up resistor, and stays low for at least tINT_Min after a valid push-button press. |
| 9 | EN | output | Active high enable output in push-pull that is asserted after a valid turn-on event to enable system power and is released low on the defined power-down conditions. |
| 10 | RST | output | Active low open-drain reset output that is pulled low for tREC during startup and after a valid long push on this variant, and requires a pull-up resistor. |
| 11 | INT | output | Active low open-drain interrupt output that is asserted for at least tINT_Min on a push-button press held for tDEBOUNCE or on undervoltage, and requires a pull-up resistor. |
| 12 | GND | power_in | Ground reference for the device. |
| 13 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TDFN-12(2x3) |
| Category | Power Management (PMIC) |
| Pins | 13 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage | VCC | 1.6 | 5.5 | V | 39 | ||
| Supply current | ICC | 6 | 8 | µA | VCC = 3.6 V, no load | 39 | |
| Standby supply current | ICC | 0.6 | 1 | µA | Standby mode, enable deasserted, VCC = 3.6 V | 39 | |
| Power-on lockout voltage (S option) | VTH+ | 3.29 | 3.4 | 3.51 | V | 39 | |
| Forced power-off voltage (S option) | VTH- | 3.2 | V | 49 | |||
| Threshold hysteresis (option 2) | VHYST | 200 | mV | 39 | |||
| Undervoltage detection to INT delay | tTH- | 20 | 32 | 44 | ms | VCC ≥ 2.0 V | 39 |
| Blanking period (5.6 s option) | tON_BLANK | 5.6 | 8.8 | 12 | s | 39 | |
| PB input low voltage | VIL | 0.99 | V | VCC ≥ 2.0 V, enable asserted | 40 | ||
| PB input high voltage | VIH | 1.05 | V | VCC ≥ 2.0 V, enable asserted | 40 | ||
| PB debounce period | tDEBOUNCE | 20 | 32 | 44 | ms | VCC ≥ 2.0 V | 40 |
| PB internal pull-up resistor | RPB | 65 | 100 | 135 | kΩ | VCC = 5.5 V, input asserted | 40 |
| SR input low voltage | VIL | 0.99 | V | 40 | |||
| SR input high voltage | VIH | 1.05 | V | 40 | |||
| SR debounce period | tDEBOUNCE | 20 | 32 | 44 | ms | 40 | |
| SR internal pull-up resistor | RSR | 65 | 100 | 135 | kΩ | VCC = 5.5 V, input asserted | 40 |
| PBOUT output low voltage | VOL | 0.3 | V | VCC = 2 V, ISINK = 1 mA, PBOUT asserted | 40 | ||
| PBOUT leakage current | -0.1 | 0.1 | µA | VPBOUT = 3 V, PBOUT open drain | 40 | ||
| VCCLO output low voltage | VOL | 0.3 | V | VCC = 2 V, ISINK = 1 mA, VCCLO asserted | 40 | ||
| VCCLO leakage current | -0.1 | 0.1 | µA | VVCCLO = 3 V, VCCLO open drain | 40 | ||
| PSHOLD input low voltage | VIL | 0.99 | V | VCC ≥ 2.0 V | 40 | ||
| PSHOLD input high voltage | VIH | 1.05 | V | VCC ≥ 2.0 V | 40 | ||
| PSHOLD leakage current | -0.1 | 0.1 | µA | VPSHOLD = 0.6 V | 40 | ||
| PSHOLD pull-down resistor (power-up) | RPSHOLD | 195 | 300 | 405 | kΩ | VPSHOLD = 5.5 V | 40 |
| CSRD charging current | ISRD | 100 | 150 | 200 | nA | 41 | |
| Additional Smart Reset delay time | tSRD | 10 | s/µF | External CSRD connected | 41 | ||
| EN output low voltage | VOL | 0.3 | V | VCC = 2 V, ISINK = 1 mA, enable asserted | 41 | ||
| enable off to enable on delay | tEN_OFF | 40 | 64 | 88 | ms | VCC ≥ 2.0 V | 41 |
| EN leakage current | -0.1 | 0.1 | µA | VEN = 2 V, enable open drain | 41 | ||
| RST output low voltage | VOL | 0.3 | V | VCC = 2 V, ISINK = 1 mA, RST asserted | 41 | ||
| RST pulse width | tREC | 240 | 360 | 480 | ms | VCC ≥ 2.0 V | 41 |
| RST leakage current | -0.1 | 0.1 | µA | VRST = 3 V | 41 | ||
| INT output low voltage | VOL | 0.3 | V | VCC = 2 V, ISINK = 1 mA, INT asserted | 41 | ||
| Minimum INT pulse width | tINT_Min | 20 | 32 | 44 | ms | VCC ≥ 2.0 V | 41 |
| INT leakage current | -0.1 | 0.1 | µA | VINT = 3 V | 41 | ||
| VREF reference voltage | VREF | 1.485 | 1.5 | 1.515 | V | VCC = 3.6 V, load on VREF pin 100 kΩ and mandatory 1 µF capacitor, TA = 25 °C | 41 |
| Supply voltage (absolute maximum) | VCC | -0.3 | 7 | V | 38 | ||
| ESD human body model (all pins) | VESD | -2 | 2 | kV | Human body model (all pins) | 38 | |
| ESD human body model (PB and SR) | VESD | -8 | 8 | kV | Human body model (PB and SR) | 38 | |
| ESD charged device model | VESD | -1000 | 1000 | V | Charged device model | 38 | |
| ESD machine model | VESD | -200 | 200 | V | Machine model | 38 | |
| ESD point discharge on PB and SR | VESD | -8 | 8 | kV | IEC61000-4-2 | 38 | |
| ESD air discharge on PB and SR | VESD | -15 | 15 | kV | IEC61000-4-2 | 38 | |
| Operating ambient temperature | TA | -40 | 85 | °C | 38 | ||
| Storage temperature | TSTG | -45 | 150 | °C | 38 | ||
| Lead solder temperature for 10 seconds | TSLD | 260 | °C | Reflow at peak temperature of 260 °C | 38 | ||
| Thermal resistance junction to ambient | θJA | 132.4 | °C/W | 38 |
CAD (KiCad official)
- Symbol:
STM6600AS24DM6F - Footprint:
Package_DFN_QFN:DFN-12-1EP_2x3mm_P0.45mm_EP0.64x2.4mm - 3D model: TDFN-12(2x3) (KiCad packages3D, STEP)
- 3D model files:
stm6600as24dm6f-etched.step/stm6600as24dm6f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm6600as24dm6f.step/stm6600as24dm6f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (52 pp, sha256
24305a688f436ae9, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).