component
STM32L452CEU6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), QFN-48-EP(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSTM32L452CEU6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · QFN-48-EP(7x7)
STM32L452CEU6 from STMicroelectronics, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup battery supply voltage (1.55 to 3.6 V) for RTC and backup registers. |
| 2 | PC13 | bidirectional | Digital I/O with alternate function EVENTOUT; RTC tamper input, timestamp, and wakeup pin. |
| 3 | PC14-OSC32_IN (PC14) | bidirectional | Digital I/O that can configure as 32 kHz oscillator input (OSC32_IN) with EVENTOUT alternate function. |
| 4 | PC15-OSC32_OUT (PC15) | bidirectional | Digital I/O that can configure as 32 kHz oscillator output (OSC32_OUT) with EVENTOUT alternate function. |
| 5 | PH0-OSC_IN (PH0) | bidirectional | |
| 6 | PH1-OSC_OUT (PH1) | bidirectional | |
| 7 | NRST | input | |
| 8 | VSSA/VREF- | power_in | Analog ground and negative reference voltage (0 V) for ADC, DAC, OPAMP, and COMP peripherals. |
| 9 | VDDA/VREF+ | power_in | Analog supply voltage (1.62 to 3.6 V) and positive reference for ADC, DAC, OPAMP, COMP, and VREFBUF. |
| 10 | PA0 | bidirectional | GPIO with alternate functions for TIM2 (CH1, ETR), USART2 (CTS), COMP1 output, SAI1 external clock, and ADC1_IN5. |
| 11 | PA1 | bidirectional | GPIO with alternate functions for TIM2 (CH2), I2C1 (SMBA), SPI1 (SCK), USART2 (RTS_DE), TIM15 (CH1N), and ADC1_IN6. |
| 12 | PA2 | bidirectional | GPIO with alternate functions for TIM2 (CH3), USART2 (TX), LPUART1 (TX), QUADSPI (BK1_NCS), TIM15 (CH1), and ADC1_IN7. |
| 13 | PA3 | bidirectional | GPIO with alternate functions for TIM2 (CH4), USART2 (RX), LPUART1 (RX), QUADSPI (CLK), SAI1 (MCLK_A), TIM15 (CH2), and ADC1_IN8. |
| 14 | PA4 | bidirectional | GPIO with alternate functions for SPI1 (NSS), SPI3 (NSS), USART2 (CK), SAI1 (FS_B), LPTIM2 (OUT), DAC1 (OUT1), and ADC1_IN9. |
| 15 | PA5 | bidirectional | GPIO with alternate functions for TIM2 (CH1, ETR), SPI1 (SCK), DFSDM1 (CKOUT), LPTIM2 (ETR), and ADC1_IN10. |
| 16 | PA6 | bidirectional | GPIO with alternate functions for TIM1 (BKIN, BKIN_COMP2), TIM3 (CH1), SPI1 (MISO), COMP1 output, USART3 (CTS), LPUART1 (CTS), QUADSPI (BK1_IO3), TIM16 (CH1), and ADC1_IN11. |
| 17 | PA7 | bidirectional | GPIO with alternate functions for TIM1 (CH1N), TIM3 (CH2), I2C3 (SCL), SPI1 (MOSI), DFSDM1 (DATIN0), QUADSPI (BK1_IO2), COMP2 output, and ADC1_IN12. |
| 18 | PB0 | bidirectional | GPIO with alternate functions for TIM1 (CH2N), TIM3 (CH3), SPI1 (NSS), DFSDM1 (CKIN0), USART3 (CK), QUADSPI (BK1_IO1), COMP1 output, SAI1 (EXTCLK), and ADC1_IN15. |
| 19 | PB1 | bidirectional | GPIO with alternate functions for TIM1 (CH3N), TIM3 (CH4), DFSDM1 (DATIN0), USART3 (RTS_DE), LPUART1 (RTS_DE), QUADSPI (BK1_IO0), LPTIM2 (IN1), and ADC1_IN16. |
| 20 | PB2 | bidirectional | GPIO with alternate functions for RTC (OUT), LPTIM1 (OUT), I2C3 (SMBA), DFSDM1 (CKIN0), and COMP1 input. |
| 21 | PB10 | bidirectional | GPIO with alternate functions for TIM2 (CH3), I2C4 (SCL), I2C2 (SCL), SPI2 (SCK), USART3 (TX), LPUART1 (RX), TSC (SYNC), QUADSPI (CLK), COMP1 output, and SAI1 (SCK_A). |
| 22 | PB11 | bidirectional | GPIO with alternate functions for TIM2 (CH4), I2C4 (SDA), I2C2 (SDA), USART3 (RX), LPUART1 (TX), QUADSPI (BK1_NCS), and COMP2 output. |
| 23 | VSS | power_in | Ground reference pin for digital logic (0 V reference). |
| 24 | VDD | power_in | Main digital supply voltage (1.71 to 3.6 V) for core and I/O logic. |
| 25 | PB12 | bidirectional | GPIO with alternate functions for TIM1 (BKIN, BKIN_COMP2), I2C2 (SMBA), SPI2 (NSS), DFSDM1 (DATIN1), USART3 (CK), LPUART1 (RTS_DE), TSC (G1_IO1), CAN1 (RX), SAI1 (FS_A), and TIM15 (BKIN). |
| 26 | PB13 | bidirectional | GPIO with alternate functions for TIM1 (CH1N), I2C2 (SCL), SPI2 (SCK), DFSDM1 (CKIN1), USART3 (CTS), LPUART1 (CTS), TSC (G1_IO2), CAN1 (TX), SAI1 (SCK_A), and TIM15 (CH1N). |
| 27 | PB14 | bidirectional | GPIO with alternate functions for TIM1 (CH2N), I2C2 (SDA), SPI2 (MISO), DFSDM1 (DATIN2), USART3 (RTS_DE), TSC (G1_IO3), SAI1 (MCLK_A), and TIM15 (CH1). |
| 28 | PB15 | bidirectional | GPIO with alternate functions for RTC (REFIN), TIM1 (CH3N), SPI2 (MOSI), DFSDM1 (CKIN2), TSC (G1_IO4), SAI1 (SD_A), and TIM15 (CH2). |
| 29 | PA8 | bidirectional | GPIO with alternate functions for MCO (master clock output), TIM1 (CH1), DFSDM1 (CKIN1), USART1 (CK), SAI1 (SCK_A), and LPTIM2 (OUT). |
| 30 | PA9 | bidirectional | GPIO with alternate functions for TIM1 (CH2), I2C1 (SCL), DFSDM1 (DATIN1), USART1 (TX), SAI1 (FS_A), and TIM15 (BKIN). |
| 31 | PA10 | bidirectional | GPIO with alternate functions for TIM1 (CH3), I2C1 (SDA), USART1 (RX), USB (CRS_SYNC), and SAI1 (SD_A). |
| 32 | PA11 | bidirectional | GPIO with alternate functions for TIM1 (CH4, BKIN2, BKIN2_COMP1), SPI1 (MISO), COMP1 output, USART1 (CTS), CAN1 (RX), and USB (DM). |
| 33 | PA12 | bidirectional | GPIO with alternate functions for TIM1 (ETR), SPI1 (MOSI), USART1 (RTS_DE), CAN1 (TX), and USB (DP). |
| 34 | PA13 (JTMS/SWDIO) | bidirectional | JTAG/SWD debug pin (SWDIO) with internal pull-up after reset; alternate functions for IR output, USB (NOE), and SAI1 (SD_B). |
| 35 | VSS | power_in | Ground reference pin for digital logic (0 V reference). |
| 36 | VDDUSB | power_in | USB supply voltage (3.0 to 3.6 V) dedicated for USB interface. |
| 37 | PA14 (JTCK/SWCLK) | bidirectional | JTAG/SWD debug pin (SWCLK) with internal pull-down after reset; alternate functions for LPTIM1 (OUT), I2C1 (SMBA), I2C4 (SMBA), and SAI1 (FS_B). |
| 38 | PA15 (JTDI) | bidirectional | JTAG debug pin (JTDI) with internal pull-up after reset; alternate functions for TIM2 (CH1, ETR), USART2 (RX), SPI1 (NSS), SPI3 (NSS), USART3 (RTS_DE), UART4 (RTS_DE), and TSC (G3_IO1). |
| 39 | PB3 (JTDO/TRACESWO) | bidirectional | JTAG debug and trace pin (JTDO/TRACESWO); alternate functions for TIM2 (CH2), SPI1 (SCK), SPI3 (SCK), USART1 (RTS_DE), and SAI1 (SCK_B); COMP2 input. |
| 40 | PB4 (NJTRST) | bidirectional | JTAG reset pin (NJTRST) for debug; alternate functions for TIM3 (CH1), I2C3 (SDA), SPI1 (MISO), SPI3 (MISO), USART1 (CTS), TSC (G2_IO1), and SAI1 (MCLK_B); COMP2 input. |
| 41 | PB5 | bidirectional | GPIO with alternate functions for LPTIM1 (IN1), TIM3 (CH2), CAN1 (RX), I2C1 (SMBA), SPI1 (MOSI), SPI3 (MOSI), USART1 (CK), TSC (G2_IO2), COMP2 output, SAI1 (SD_B), and TIM16 (BKIN). |
| 42 | PB6 | bidirectional | GPIO with alternate functions for LPTIM1 (ETR), I2C1 (SCL), I2C4 (SCL), USART1 (TX), CAN1 (TX), TSC (G2_IO3), SAI1 (FS_B), and TIM16 (CH1N); COMP2 input. |
| 43 | PB7 | bidirectional | GPIO with alternate functions for LPTIM1 (IN2), I2C1 (SDA), I2C4 (SDA), USART1 (RX), UART4 (CTS), TSC (G2_IO4); COMP2 input and PVD input. |
| 44 | PH3-BOOT0 (BOOT0) | bidirectional | Boot mode selection pin for device startup; GPIO with EVENTOUT alternate function. |
| 45 | PB8 | bidirectional | GPIO with alternate functions for I2C1 (SCL), CAN1 (RX), SDMMC1 (D4), SAI1 (MCLK_A), and TIM16 (CH1). |
| 46 | PB9 | bidirectional | GPIO with alternate functions for IR output, I2C1 (SDA), SPI2 (NSS), CAN1 (TX), SDMMC1 (D5), and SAI1 (FS_A). |
| 47 | VSS | power_in | Ground reference pin for digital logic (0 V reference). |
| 48 | VDD | power_in | Main digital supply voltage (1.71 to 3.6 V) for core and I/O logic. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | QFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
STM32L452CEU6 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32l452ceu6-etched.step/stm32l452ceu6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l452ceu6.step/stm32l452ceu6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (210 pp, sha256
eeeaa72ec16c85ea, retrieved 2026-09-29, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).