component
STM32L151RCT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32L151RCT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32L151RCT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VLCD | power_in | LCD voltage supply; for STM32L151xC (no LCD controller) datasheet footnote 3 requires this pin be connected to VDD; max 3.6 V. |
| 2 | PC13-WKUP2 | bidirectional | 5 V tolerant GPIO PC13; additional functions: WKUP2 wakeup from Standby, RTC_TAMP1, RTC_TS, RTC_OUT; floating input after reset. |
| 3 | PC14-OSC32_IN | bidirectional | Standard 3.3 V GPIO PC14; shared with LSE 32.768 kHz oscillator input OSC32_IN when LSE is enabled (LSEON bit set); LSE has priority over GPIO. |
| 4 | PC15-OSC32_OUT | bidirectional | Standard 3.3 V GPIO PC15; shared with LSE 32.768 kHz oscillator output OSC32_OUT when LSE is enabled; LSE has priority over GPIO. |
| 5 | PH0-OSC_IN | bidirectional | Standard 3.3 V GPIO PH0; shared with HSE oscillator input OSC_IN (1-24 MHz) when HSE is enabled (HSEON bit set); HSE has priority over GPIO. |
| 6 | PH1-OSC_OUT | bidirectional | Standard 3.3 V GPIO PH1; shared with HSE oscillator output OSC_OUT when HSE is enabled; HSE has priority over GPIO. |
| 7 | NRST | bidirectional | Active-low reset; bidirectional with embedded 25-65 kΩ pull-up; filters pulses below 50 ns; VIL max = 0.3 VDD, VIH min = 0.39 VDD + 0.59 V; VOL max = 0.4 V at IOL = 2 mA. |
| 8 | PC0 | bidirectional | 5 V tolerant GPIO PC0; alternate: LCD_SEG18; additional: ADC_IN10, COMP1_INP; floating input after reset. |
| 9 | PC1 | bidirectional | 5 V tolerant GPIO PC1; alternate: LCD_SEG19; additional: ADC_IN11, COMP1_INP; floating input after reset. |
| 10 | PC2 | bidirectional | 5 V tolerant GPIO PC2; alternate: LCD_SEG20; additional: ADC_IN12, COMP1_INP; floating input after reset. |
| 11 | PC3 | bidirectional | Standard 3.3 V GPIO PC3; alternate: LCD_SEG21; additional: ADC_IN13, COMP1_INP; floating input after reset. |
| 12 | VSSA | power_in | Analog ground reference for ADC, DAC, comparators, and PLL; must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply voltage 1.65-3.6 V (minimum 1.8 V when ADC or DAC is used); must be same voltage as VDD within 300 mV in operation. |
| 14 | PA0-WKUP1 | bidirectional | 5 V tolerant GPIO PA0; additional: WKUP1 wakeup from Standby, RTC_TAMP2, ADC_IN0, COMP1_INP; alternate: TIM2_CH1_ETR, TIM5_CH1, USART2_CTS. |
| 15 | PA1 | bidirectional | 5 V tolerant GPIO PA1; alternate: TIM2_CH2, TIM5_CH2, USART2_RTS, LCD_SEG0; additional: ADC_IN1, COMP1_INP, OPAMP1_VINP. |
| 16 | PA2 | bidirectional | 5 V tolerant GPIO PA2; alternate: TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, LCD_SEG1; additional: ADC_IN2, COMP1_INP, OPAMP1_VINM. |
| 17 | PA3 | bidirectional | Standard 3.3 V GPIO PA3; alternate: TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, LCD_SEG2; additional: ADC_IN3, COMP1_INP, OPAMP1_VOUT. |
| 18 | VSS_4 | power_in | Digital ground reference; must be connected to system ground; total sink current across all VSS pins ≤ 100 mA, per pin ≤ 70 mA. |
| 19 | VDD_4 | power_in | Main digital supply 1.65-3.6 V (BOR disabled) or 1.8-3.6 V (BOR enabled); source current per pin ≤ 70 mA, total across all VDD pins ≤ 100 mA. |
| 20 | PA4 | bidirectional | Standard 3.3 V GPIO PA4; alternate: SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK; additional: ADC_IN4, DAC_OUT1, COMP1_INP. |
| 21 | PA5 | bidirectional | Standard 3.3 V GPIO PA5; alternate: TIM2_CH1_ETR, SPI1_SCK; additional: ADC_IN5, DAC_OUT2, COMP1_INP. |
| 22 | PA6 | bidirectional | 5 V tolerant GPIO PA6; alternate: TIM3_CH1, TIM10_CH1, SPI1_MISO, LCD_SEG3; additional: ADC_IN6, COMP1_INP, OPAMP2_VINP. |
| 23 | PA7 | bidirectional | 5 V tolerant GPIO PA7; alternate: TIM3_CH2, TIM11_CH1, SPI1_MOSI, LCD_SEG4; additional: ADC_IN7, COMP1_INP, OPAMP2_VINM. |
| 24 | PC4 | bidirectional | 5 V tolerant GPIO PC4; alternate: LCD_SEG22; additional: ADC_IN14, COMP1_INP; floating input after reset. |
| 25 | PC5 | bidirectional | 5 V tolerant GPIO PC5; alternate: LCD_SEG23; additional: ADC_IN15, COMP1_INP; floating input after reset. |
| 26 | PB0 | bidirectional | Standard 3.3 V GPIO PB0; alternate: TIM3_CH3, LCD_SEG5; additional: ADC_IN8, COMP1_INP, OPAMP2_VOUT, VLCDRAIL3, VREF_OUT. |
| 27 | PB1 | bidirectional | 5 V tolerant GPIO PB1; alternate: TIM3_CH4, LCD_SEG6; additional: ADC_IN9, COMP1_INP, VREF_OUT. |
| 28 | PB2 | bidirectional | 5 V tolerant GPIO PB2; sampled at reset as BOOT1 to determine boot memory source in combination with BOOT0; additional: VLCDRAIL1. |
| 29 | PB10 | bidirectional | 5 V tolerant GPIO PB10; alternate: TIM2_CH3, I2C2_SCL, USART3_TX, LCD_SEG10; floating input after reset. |
| 30 | PB11 | bidirectional | 5 V tolerant GPIO PB11; alternate: TIM2_CH4, I2C2_SDA, USART3_RX, LCD_SEG11; floating input after reset. |
| 31 | VSS_1 | power_in | Digital ground reference; must be connected to system ground; total sink current across all VSS pins ≤ 100 mA, per pin ≤ 70 mA. |
| 32 | VDD_1 | power_in | Main digital supply 1.65-3.6 V (BOR disabled) or 1.8-3.6 V (BOR enabled); source current per pin ≤ 70 mA, total across all VDD pins ≤ 100 mA. |
| 33 | PB12 | bidirectional | 5 V tolerant GPIO PB12; alternate: TIM10_CH1, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, LCD_SEG12; additional: ADC_IN18, VLCDRAIL2. |
| 34 | PB13 | bidirectional | 5 V tolerant GPIO PB13; alternate: TIM9_CH1, SPI2_SCK/I2S2_CK, USART3_CTS, LCD_SEG13; additional: ADC_IN19, COMP1_INP. |
| 35 | PB14 | bidirectional | 5 V tolerant GPIO PB14; alternate: TIM9_CH2, SPI2_MISO, USART3_RTS, LCD_SEG14; additional: ADC_IN20, COMP1_INP. |
| 36 | PB15 | bidirectional | 5 V tolerant GPIO PB15; alternate: TIM11_CH1, SPI2_MOSI/I2S2_SD, LCD_SEG15; additional: ADC_IN21, COMP1_INP, RTC_REFIN. |
| 37 | PC6 | bidirectional | 5 V tolerant GPIO PC6; alternate: TIM3_CH1, I2S2_MCK, LCD_SEG24; floating input after reset. |
| 38 | PC7 | bidirectional | 5 V tolerant GPIO PC7; alternate: TIM3_CH2, I2S3_MCK, LCD_SEG25; floating input after reset. |
| 39 | PC8 | bidirectional | 5 V tolerant GPIO PC8; alternate: TIM3_CH3, LCD_SEG26; floating input after reset. |
| 40 | PC9 | bidirectional | 5 V tolerant GPIO PC9; alternate: TIM3_CH4, LCD_SEG27; floating input after reset. |
| 41 | PA8 | bidirectional | 5 V tolerant GPIO PA8; alternate: USART1_CK, MCO (microcontroller clock output), LCD_COM0; floating input after reset. |
| 42 | PA9 | bidirectional | 5 V tolerant GPIO PA9; alternate: USART1_TX, LCD_COM1; floating input after reset. |
| 43 | PA10 | bidirectional | 5 V tolerant GPIO PA10; alternate: USART1_RX, LCD_COM2; floating input after reset. |
| 44 | PA11 | bidirectional | 5 V tolerant GPIO PA11; alternate: USART1_CTS, SPI1_MISO; additional: USB_DM (USB 2.0 full-speed 12 Mbit/s D− line); USB requires VDD ≥ 3.0 V. |
| 45 | PA12 | bidirectional | 5 V tolerant GPIO PA12; alternate: USART1_RTS, SPI1_MOSI; additional: USB_DP (USB 2.0 full-speed 12 Mbit/s D+ line); USB requires VDD ≥ 3.0 V. |
| 46 | PA13 | bidirectional | 5 V tolerant GPIO PA13; default function after reset is JTMS-SWDIO (JTAG/SWD data I/O shared with TMS); remappable to GPIO via AFIO. |
| 47 | VSS_2 | power_in | Digital ground reference; must be connected to system ground; total sink current across all VSS pins ≤ 100 mA, per pin ≤ 70 mA. |
| 48 | VDD_2 | power_in | Main digital supply 1.65-3.6 V (BOR disabled) or 1.8-3.6 V (BOR enabled); source current per pin ≤ 70 mA, total across all VDD pins ≤ 100 mA. |
| 49 | PA14 | bidirectional | 5 V tolerant GPIO PA14; default function after reset is JTCK-SWCLK (JTAG TCK / SWD clock shared with TCK); remappable to GPIO via AFIO. |
| 50 | PA15 | bidirectional | 5 V tolerant GPIO PA15; default function after reset is JTDI (JTAG data input); alternate: TIM2_CH1_ETR, SPI1_NSS, SPI3_NSS/I2S3_WS, LCD_SEG17. |
| 51 | PC10 | bidirectional | 5 V tolerant GPIO PC10; alternate: SPI3_SCK/I2S3_CK, USART3_TX, LCD_COM4/SEG28/SEG40; floating input after reset. |
| 52 | PC11 | bidirectional | 5 V tolerant GPIO PC11; alternate: SPI3_MISO, USART3_RX, LCD_COM5/SEG29/SEG41; floating input after reset. |
| 53 | PC12 | bidirectional | 5 V tolerant GPIO PC12; alternate: SPI3_MOSI/I2S3_SD, USART3_CK, LCD_COM6/SEG30/SEG42; floating input after reset. |
| 54 | PD2 | bidirectional | 5 V tolerant GPIO PD2; alternate: TIM3_ETR, LCD_COM7/SEG31/SEG43; floating input after reset. |
| 55 | PB3 | bidirectional | 5 V tolerant GPIO PB3; default function after reset is JTDO (JTAG data output); alternate: TIM2_CH2, SPI1_SCK, SPI3_SCK/I2S3_CK, LCD_SEG7; additional: COMP2_INM. |
| 56 | PB4 | bidirectional | 5 V tolerant GPIO PB4; default function after reset is NJTRST (JTAG reset); alternate: TIM3_CH1, SPI1_MISO, SPI3_MISO, LCD_SEG8; additional: COMP2_INP. |
| 57 | PB5 | bidirectional | 5 V tolerant GPIO PB5; alternate: TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, LCD_SEG9; additional: COMP2_INP. |
| 58 | PB6 | bidirectional | 5 V tolerant GPIO PB6; alternate: TIM4_CH1, I2C1_SCL, USART1_TX; additional: COMP2_INP. |
| 59 | PB7 | bidirectional | 5 V tolerant GPIO PB7; alternate: TIM4_CH2, I2C1_SDA, USART1_RX; additional: COMP2_INP, PVD_IN. |
| 60 | BOOT0 | input | Dedicated boot-mode selection input; sampled at reset to select Flash, System memory, or embedded RAM boot; input range 0-5.5 V; VIL max = 0.14 VDD, VIH min = 0.15 VDD + 0.56 V. |
| 61 | PB8 | bidirectional | 5 V tolerant GPIO PB8; alternate: TIM4_CH3, TIM10_CH1, I2C1_SCL, LCD_SEG16; floating input after reset. |
| 62 | PB9 | bidirectional | 5 V tolerant GPIO PB9; alternate: TIM4_CH4, TIM11_CH1, I2C1_SDA, LCD_COM3; floating input after reset. |
| 63 | VSS_3 | power_in | Digital ground reference; must be connected to system ground; total sink current across all VSS pins ≤ 100 mA, per pin ≤ 70 mA. |
| 64 | VDD_3 | power_in | Main digital supply 1.65-3.6 V (BOR disabled) or 1.8-3.6 V (BOR enabled); source current per pin ≤ 70 mA, total across all VDD pins ≤ 100 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32L151RCT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32l151rct6-etched.step/stm32l151rct6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l151rct6.step/stm32l151rct6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (136 pp, sha256
5e6d5674cd06c108, retrieved 2026-09-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).