STM32G431CBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32G431CBT6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol and footprint from KiCad-official CAD; the 3D model comes from KiCad's own package generator at the datasheet's values and carries ST's real top marking.

Pinout

Key specifications

Ordering variants

Same part, different packaging or reel option.

• STM32G431CBT6
• STM32G431CBT6C8T6
• STM32G431CBT6C6T6
• STM32G431CBT6CBT3
• STM32G431CBT6CBU6
• STM32G431CBT6C8U6
• STM32G431CBT6C6U6
• STM32G431CBT6K6U6
• STM32G431CBT6K8U6
• STM32G431CBT6KBU6
• STM32G431CBT6R6T6
• STM32G431CBT6R8T6
• STM32G431CBT6RBT6
• STM32G431CBT6RBI6
• STM32G431CBT6M6T6
• STM32G431CBT6M8T6
• STM32G431CBT6MBT6
• STM32G431CBT6V6T6
• STM32G431CBT6V8T6
• STM32G431CBT6VBT6

CAD

• Symbol: STM32G431CBT6 (KiCad, adom-symbol 1.2.6, intelligent pin groups, chip outline baked in the body)
• Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm (KiCad official)
• Fusion / EAGLE: stm32g431cbt6.lbr

Top marking (the real one, from the datasheet)

Every 3D file on this page that carries a marking carries the manufacturer's own top marking, not an invented label:

The datasheet's marking figure (p.177):

3D models

Frame for every file: Z up, seated on z = 0, centred on the KiCad footprint origin, pin 1 on footprint pad 1, binds with zero offset and rotation.

How the model is made (2026-10-21): with KiCad's own package generator (kicad-packages3D-generator, the CadQuery scripts behind KiCad's 3D library), so the leads have KiCad's real radiused gull-wing bends, run with the datasheet's values instead of the library's generic ones. ST DS12589 Table 94 typical values: D = E 9.00, D1 = E1 7.00, A1 0.10, A2 1.40 (A 1.50), b 0.22, e 0.50, L 0.60 to the gauge plane; c 0.145 (midpoint of 0.09 to 0.20: no typical printed); KiCad's bend radii R1 = R2 = 0.10 (JEDEC MS-026 range), body draft 12 deg and edge fillet 0.05.

Why not KiCad's library model as it is: KiCad's shipped STEP is 6 um under ST's 0.45 mm minimum. KiCad's current generator, run with its own LQFP-48 parameters, already gives 0.600 mm; it was run with ST Table 94's typical values. Measured L foot to the 0.25 mm gauge plane: datasheet 0.45 / 0.60 / 0.75, KiCad library 0.444, regenerated 0.600 mm. Method: section through one lead's centre line (plane y = lead centre), cut at the 0.25 mm gauge plane (z = 0.25); L = distance from the lead tip to where the lead's lower outer surface crosses the gauge plane (JEDEC definition), provenance/tools/kicad-generator/measure.py.

Leads: before and after

The page carried a hand-built model with square 90 degree lead folds from 2026-10-19 to 2026-10-21. It is replaced by the generator's radiused bends, with the leads in their own matte-tin material:

Model proof: overlay on the datasheet drawing

The plain model was rendered orthographically at the drawing's own scale and blended over the datasheet's top and side/end views. Red outline and blue fill: the model. Black lines: the datasheet.

Pin 1: KiCad's pin-1 dimple (generator default) replaces the former 0.75 mm dimple; ST's figure shows a pin-1 identification circle at that corner. The marking was re-applied with the same reviewed inputs: etched with --over-vendor-mark: the generated body has no printed marking, but its 0.05 mm top edge fillets read as glyph faces to the vendor-mark detector; the date and revision codes were added with provenance/tools/extra_marks.py exactly as before.

Cited datasheet pages:

Detail levels for board and digital-twin viewers

All four levels come from the generated model, share the Z-up frame, units and seating of the library model, carry no footprint or silkscreen artwork, and keep the real terminals and the pin-1 cue. High is the marked model with its primitives batched per part (geometry unchanged); medium is the same, quantized; low and super-low are error-bounded simplifications without the marking (unreadable at those sizes). Status: candidate; the cached previews were inspected, a streaming LOD viewer has not qualified them.

Symbol chip outline

The symbol body carries the chip outline, so the schematic shows the same chip and marking as the 3D view. It was redrawn on 2026-10-21 from the new model: artwork/STM32G431CBT6-3d-outline-dark-named.svg, drawn from the marked model in adom-aiflow-etch outline's standard pose: the service draws the body outline and the name is the etched model's own mark edges, projected with the tool's calibration (provenance/tools/kicad-generator/mark_art.py); the tool's outline gate passes. adom-aiflow-etch outline itself now only composes a single-stroke name, which drops parts of the real mark here (ST's Y WW / R codes). The KiCad symbol and the Fusion library (.lbr) carry the same drawing.

3D model provenance

provenance/3d-model.json records the datasheet (document, revision, pages, SHA-256), every model dimension against the datasheet, what was measured off the drawing, the generator, its parameters and the measurement (provenance/tools/kicad-generator/), the etch gate result, file hashes, tool versions and the AI-derived classification. PROVENANCE.md is the readable summary.

Datasheet provenance

• Datasheet: ST DS12589 Rev 2 (October 2019), STM32G431x6/x8/xB datasheet (PDF, sha256 cabefb21b47dc4c1). The PDF's metadata title names STM32G474; the document itself is DS12589, the STM32G431 datasheet.
• Pins: extracted by ds2sf (Claude); every pin cites a datasheet page.