STM32G431CBT6 - Arm Cortex-M4 Microcontroller
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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README
markdownSTM32G431CBT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM32G431CBT6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup supply for RTC and backup registers when VDD is off. Connect to VDD or a battery (1.55 V to 3.6 V). |
| 2 | PC13 | bidirectional | General-purpose 5V-tolerant I/O in Backup domain (limited drive: max 2 MHz / 30 pF via power switch). Alternate: TIM1_BKIN, TIM1_CH1N, TIM8_CH4N, EVENTOUT. Additional: WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT1. |
| 3 | PC14-OSC32_IN | bidirectional | Backup-domain 5V-tolerant GPIO doubling as LSE 32.768 kHz crystal input (OSC32_IN). Same drive limits as PC13. |
| 4 | PC15-OSC32_OUT | bidirectional | Backup-domain 5V-tolerant GPIO doubling as LSE 32.768 kHz crystal output (OSC32_OUT). Same drive limits as PC13. |
| 5 | PF0-OSC_IN | input | HSE crystal oscillator input (OSC_IN), 4-48 MHz, or input-only 5V-tolerant Fm+ I/O PF0. Alternate: I2C2_SDA, SPI2_NSS/I2S2_WS, TIM1_CH3N, EVENTOUT. Additional: ADC1_IN10. |
| 6 | PF1-OSC_OUT | output | HSE crystal oscillator output (OSC_OUT) or output-only 5V-tolerant I/O PF1. Alternate: SPI2_SCK/I2S2_CK, EVENTOUT. Additional: ADC2_IN10, COMP3_INM. |
| 7 | PG10-NRST | bidirectional | Bidirectional device reset with embedded weak pull-up (active low). Also selectable as GPIO PG10 with MCO/EVENTOUT alternate. |
| 8 | PA0 | bidirectional | 3.6 V tolerant analog-capable I/O (TT_a). Alternate: TIM2_CH1, USART2_CTS, COMP1_OUT, TIM8_BKIN/ETR, TIM2_ETR, EVENTOUT. Additional: ADC12_IN1, COMP1_INM, COMP3_INP, RTC_TAMP2, WKUP1. |
| 9 | PA1 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM2_CH2, USART2_RTS_DE, TIM15_CH1N, EVENTOUT. Additional: RTC_REFIN, ADC12_IN2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP. |
| 10 | PA2 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM2_CH3, USART2_TX, COMP2_OUT, TIM15_CH1, LPUART1_TX, UCPD1_FRSTX, EVENTOUT. Additional: ADC1_IN3, COMP2_INM, OPAMP1_VOUT, WKUP4/LSCO. |
| 11 | PA3 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM2_CH4, SAI1_CK1, USART2_RX, TIM15_CH2, LPUART1_RX, SAI1_MCLK_A, EVENTOUT. Additional: ADC1_IN4, COMP2_INP, OPAMP1_VINM/VINP. |
| 12 | PA4 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM3_CH2, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, SAI1_FS_B, EVENTOUT. Additional: ADC2_IN17, DAC1_OUT1, COMP1_INM. |
| 13 | PA5 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM2_CH1, TIM2_ETR, SPI1_SCK, UCPD1_FRSTX, EVENTOUT. Additional: ADC2_IN13, DAC1_OUT2, COMP2_INM, OPAMP2_VINM. |
| 14 | PA6 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM16_CH1, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM1_BKIN, COMP1_OUT, LPUART1_CTS, EVENTOUT. Additional: ADC2_IN3, OPAMP2_VOUT. |
| 15 | PA7 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM17_CH1, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM1_CH1N, COMP2_OUT, UCPD1_FRSTX, EVENTOUT. Additional: ADC2_IN4, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP. |
| 16 | PB0 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UCPD1_FRSTX, EVENTOUT. Additional: ADC1_IN15, COMP4_INP, OPAMP2_VINP, OPAMP3_VINP. |
| 17 | PB1 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM3_CH4, TIM8_CH3N, TIM1_CH3N, COMP4_OUT, LPUART1_RTS_DE, EVENTOUT. Additional: ADC1_IN12, COMP1_INP, OPAMP3_VOUT. |
| 18 | PB2 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: RTC_OUT2, LPTIM1_OUT, I2C3_SMBA, EVENTOUT. Additional: ADC2_IN12, COMP4_INM, OPAMP3_VINM. |
| 19 | VSSA | power_in | Analog ground reference for ADC/DAC/comparators/OPAMP/VREF. Tie to system ground plane. |
| 20 | VREF+ | power_in | Positive reference voltage for ADC and DAC, or output of the internal VREFBUF (2.048 V / 2.5 V / 2.95 V). Bypass close to the pin. |
| 21 | VDDA | power_in | Analog supply for ADC/DAC/comparators/OPAMPs/VREFBUF, 1.71 V to 3.6 V. Must be present and stable before enabling analog blocks. |
| 22 | PB10 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM2_CH3, USART3_TX, LPUART1_RX, TIM1_BKIN, SAI1_SCK_A, EVENTOUT. Additional: OPAMP3_VINM. |
| 23 | VSS | power_in | Digital ground. Tie to system ground plane. |
| 24 | VDD | power_in | Main digital supply, 1.71 V to 3.6 V. Decouple locally with 100 nF and share bulk cap with the other VDD pins. |
| 25 | PB11 | bidirectional | 5 V tolerant analog-capable I/O. Alternate: TIM2_CH4, USART3_RX, LPUART1_TX, EVENTOUT. Additional: ADC12_IN14. |
| 26 | PB12 | bidirectional | 5 V tolerant analog-capable I/O. Alternate: I2C2_SMBA, SPI2_NSS/I2S2_WS, TIM1_BKIN, USART3_CK, LPUART1_RTS_DE, EVENTOUT. Additional: ADC1_IN11. |
| 27 | PB13 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS, LPUART1_CTS, EVENTOUT. Additional: OPAMP3_VINP. |
| 28 | PB14 | bidirectional | 3.6 V tolerant analog-capable I/O. Alternate: TIM15_CH1, SPI2_MISO, TIM1_CH2N, USART3_RTS_DE, COMP4_OUT, EVENTOUT. Additional: ADC1_IN5, OPAMP2_VINP. |
| 29 | PB15 | bidirectional | 5 V tolerant analog-capable I/O. Alternate: RTC_REFIN, TIM15_CH2, TIM15_CH1N, COMP3_OUT, TIM1_CH3N, SPI2_MOSI/I2S2_SD, EVENTOUT. Additional: ADC2_IN15. |
| 30 | PA8 | bidirectional | 5 V tolerant Fm+ I/O. Alternate: MCO, I2C3_SCL, I2C2_SDA, I2S2_MCK, TIM1_CH1, USART1_CK, TIM4_ETR, SAI1_CK2, SAI1_SCK_A, EVENTOUT. |
| 31 | PA9 | bidirectional | 5 V tolerant Fm+ USB Type-C dead-battery-capable I/O. Alternate: I2C3_SMBA, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX, TIM15_BKIN, TIM2_CH3, SAI1_FS_A, EVENTOUT. Additional: UCPD1_DBCC1. |
| 32 | PA10 | bidirectional | 5 V tolerant USB Type-C dead-battery-capable analog-capable I/O. Alternate: TIM17_BKIN, USB_CRS_SYNC, I2C2_SMBA, SPI2_MISO, TIM1_CH3, USART1_RX, TIM2_CH4, TIM8_BKIN, SAI1_D1/SD_A, EVENTOUT. Additional: UCPD1_DBCC2. |
| 33 | PA11 | bidirectional | USB full-speed D- (USB_DM) additional function; also 5 V tolerant I/O with alternates SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, COMP1_OUT, FDCAN1_RX, TIM4_CH1, TIM1_CH4, TIM1_BKIN2, EVENTOUT. |
| 34 | PA12 | bidirectional | USB full-speed D+ (USB_DP) additional function; also 5 V tolerant I/O with alternates TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, FDCAN1_TX, TIM4_CH2, TIM1_ETR, EVENTOUT. |
| 35 | VSS | power_in | Digital ground. Tie to system ground plane. |
| 36 | VDD | power_in | Main digital supply, 1.71 V to 3.6 V. Decouple locally with 100 nF. |
| 37 | PA13 | bidirectional | SWDIO / JTMS debug pin (default after reset, weak pull-up). Also 5 V tolerant Fm+ I/O with alternates TIM16_CH1N, I2C1_SCL, IR_OUT, USART3_CTS, TIM4_CH3, SAI1_SD_B, EVENTOUT. |
| 38 | PA14 | bidirectional | SWCLK / JTCK debug pin (default after reset, internal pull-down). Also 5 V tolerant Fm+ I/O with alternates LPTIM1_OUT, I2C1_SDA, TIM8_CH2, TIM1_BKIN, USART2_TX, SAI1_FS_B, EVENTOUT. |
| 39 | PA15 | bidirectional | JTDI debug pin at reset (weak pull-up); reconfigurable to 5 V tolerant Fm+ GPIO with alternates TIM2_CH1, TIM8_CH1, I2C1_SCL, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_RX, UART4_RTS_DE, TIM1_BKIN, TIM2_ETR, EVENTOUT. |
| 40 | PB3 | bidirectional | JTDO/TRACESWO debug pin at reset; also 5 V tolerant I/O with alternates TIM2_CH2, TIM4_ETR, USB_CRS_SYNC, TIM8_CH1N, SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX, TIM3_ETR, SAI1_SCK_B, EVENTOUT. |
| 41 | PB4 | bidirectional | JTRST debug pin at reset; also 5 V tolerant USB Type-C capable I/O with alternates TIM16_CH1, TIM3_CH1, TIM8_CH2N, SPI1_MISO, SPI3_MISO, USART2_RX, TIM17_BKIN, SAI1_MCLK_B, EVENTOUT. Additional: UCPD1_CC2. |
| 42 | PB5 | bidirectional | 5 V tolerant Fm+ I/O. Alternate: TIM16_BKIN, TIM3_CH2, TIM8_CH3N, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA, TIM17_CH1, LPTIM1_IN1, SAI1_SD_B, EVENTOUT. |
| 43 | PB6 | bidirectional | 5 V tolerant USB Type-C capable I/O. Alternate: TIM16_CH1N, TIM4_CH1, TIM8_CH1, TIM8_ETR, USART1_TX, COMP4_OUT, TIM8_BKIN2, LPTIM1_ETR, SAI1_FS_B, EVENTOUT. Additional: UCPD1_CC1. |
| 44 | PB7 | bidirectional | 5 V tolerant Fm+ I/O. Alternate: TIM17_CH1N, TIM4_CH2, I2C1_SDA, TIM8_BKIN, USART1_RX, COMP3_OUT, TIM3_CH4, LPTIM1_IN2, UART4_CTS, EVENTOUT. Additional: PVD_IN. |
| 45 | PB8-BOOT0 | bidirectional | Dedicated BOOT0 selection pin at power-up (samples boot mode); afterwards a 5 V tolerant Fm+ GPIO PB8 with alternates TIM16_CH1, TIM4_CH3, SAI1_CK1, I2C1_SCL, USART3_RX, COMP1_OUT, FDCAN1_RX, TIM8_CH2, TIM1_BKIN, SAI1_MCLK_A, EVENTOUT. |
| 46 | PB9 | bidirectional | 5 V tolerant Fm+ I/O. Alternate: TIM17_CH1, TIM4_CH4, SAI1_D2, I2C1_SDA, IR_OUT, USART3_TX, COMP2_OUT, FDCAN1_TX, TIM8_CH3, TIM1_CH3N, SAI1_FS_A, EVENTOUT. |
| 47 | VSS | power_in | Digital ground. Tie to system ground plane. |
| 48 | VDD | power_in | Main digital supply, 1.71 V to 3.6 V. Decouple locally with 100 nF. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | MCU |
| Pins | 48 |
Ordering variants
Same part, different packaging or reel option.
STM32G431CBT6STM32G431CBT6C8T6STM32G431CBT6C6T6STM32G431CBT6CBT3STM32G431CBT6CBU6STM32G431CBT6C8U6STM32G431CBT6C6U6STM32G431CBT6K6U6STM32G431CBT6K8U6STM32G431CBT6KBU6STM32G431CBT6R6T6STM32G431CBT6R8T6STM32G431CBT6RBT6STM32G431CBT6RBI6STM32G431CBT6M6T6STM32G431CBT6M8T6STM32G431CBT6MBT6STM32G431CBT6V6T6STM32G431CBT6V8T6STM32G431CBT6VBT6
CAD (KiCad official)
- Symbol:
STM32G431CBT6 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32g431cbt6-etched.step/stm32g431cbt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32g431cbt6.step/stm32g431cbt6.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
stm32g431cbt6.step |
617 KB | You want the bare part, or you mark your own boards. |
stm32g431cbt6-etched.step |
4.8 MB | You want the part with STM32G431CBT6 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1196 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (200 pp, sha256
cabefb21b47dc4c1, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
CAD provenance and independent review
Audit by Codex Astra (AI). Per-file provenance, sources and checks documents the current file hashes, source or generation inputs, modifications, verification limits and unknown origins. AI-created models are identified explicitly; a wiki upload is not manufacturer verification.
Unresolved original provenance: symbol, footprint, step, glb. See the record before treating these as source-verified assets.
Report a component problem with the filename/hash and evidence.
Optional MPN-marked model, preview and provenance
Displayed model and review status
The main 3D viewer uses stm32g431cbt6-hero-mpn.glb, derived from the reviewed stm32g431cbt6-mpn.glb. The exact MPN is AI-added identification artwork, not a factory marking. Marking inputs, fit and licensing and source provenance remain applicable.
The hero applies only a 180-degree Z display rotation; no geometry is scaled. Use the original-frame marked STEP/GLB downloads for board assemblies. The rendered package and readable mark were reviewed; that does not establish manufacturer-exact dimensions, polarity, or native-tool qualification. Binding and file hashes.
Footprint-aware inspection hero
The current hero adds separate nonphysical reference layers: teal dashed copper boundaries at 50% opacity, silkscreen at 30% opacity and actual symbol pin names (unique pad numbers when unnamed) at 50% opacity. Orbit underneath to compare physical terminals, copper and pin1 marks. Copper outlines are not soldermask/paste. Existing MPN, materials, animations and lights are preserved. These helpers are excluded from board-use STEP/GLB files. Geometry, mapping and source hashes; pin-map input. Physical body can occlude seating-plane artwork; inspect the underside or isolate it. Generated display-font contours are not native fab artwork.