component

STM32G0B1KBU6

Public Made by Adom

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STMicroelectronics Microcontrollers, UFQFPN-32(5x5). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.

componentembedded processors & controllersstm32g0b1kbu6board-derived

Verified STM32G0B1KBU6

by Claude, at Caleb Taylor's request · last 28 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 6 records

28 Oct 2026Claude, at Caleb Taylor's requestValidated against ST's STM32G0B1xB/xC/xE datasheet DS13560 Rev 6 (February 2026)files match
SymbolFootprint3D modelPinsfor all variants
  • ✓Datasheet: replaced the LCSC copy (DS13560 Rev 3, January 2022) with ST's current DS13560 Rev 6, February 2026, from st.com
  • ✓Variant: STM32G0B1KBU6 = K 32 pins, B 128 KB, U UFQFPN, 6 = -40 to 85 C, no N option, so the GP pinout applies (ordering information p.161; N-suffix devices are the alternative pinout, p.11)
  • ✓All 33 pins match Figure 4 'STM32G0B1KxU UFQFPN32 pinout', GP version (p.37) and the LQFP32/UFQFPN32-GP column of Table 12 (p.47-55) by number and name, including PC14-OSC32_IN, PC15-OSC32_OUT, VDD/VDDA, VSS/VSSA, PF2-NRST, PA11 [PA9], PA12 [PA10], PA14-BOOT0; pin 33 is the exposed pad, labelled VSS in Figure 4. No renames needed
  • ✓Pin types agree with Table 12: the 30 port pins are I/O (bidirectional; PF2-NRST is RST/FT), VDD/VDDA and VSS/VSSA are supply (power_in); exposed pad 33 changed passive -> power_in (VSS ground)
  • ✓All 33 descriptions rewritten from Table 12 rows (I/O structure decoded with Table 11 p.46, alternate and additional functions, notes 1-6 on p.55), the power supply scheme (p.17) and Figure 4; citations re-pointed from Rev 3 to Rev 6 pages
  • •Footprint (designer custom STM_CDT UFQFPN-32-1EP 5x5) vs Figure 41/Table 83 (p.130-131) and Figure 42 footprint example (p.133): 32 pads 0.25 mm wide on e = 0.50 mm, as Figure 42; pads 0.875 mm long with centres at +/-2.4375 mm (span 2.00 to 2.875 mm from centre) vs Figure 42's 0.65 mm pads in a 5.50 mm outline (2.10 to 2.75 mm): longer by 0.10 mm inward and 0.125 mm outward, still covering the terminals (D/2 = 2.50, L 0.30-0.50, b 0.18-0.30) with 0.25 mm clearance to the exposed pad; exposed pad 3.50 x 3.50 mm = Figure 42 and D2/E2 typ (3.40-3.60), with four 1.41 mm paste windows; pin 1 at the top of the left column, numbering counter-clockwise as Figure 42
  • ✓3D model rebuilt (tier 3): the previous model was extracted from a board STEP with no licence. Tier 1 unusable (ST's CAD sits behind a my.st.com login/e-mail validation via SamacSys/Ultra Librarian, whose terms forbid library redistribution); tier 2 unusable (KiCad has no UFQFPN-32 EP3.5 model; QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm is 0.77 mm tall vs A 0.50-0.60). Generated with kicad-footprint-generator @ 6ef68694 package/no_lead at DS13560 Table 83 values (patch in provenance/tools), CC-BY-SA-4.0
  • ✓3D body vs Figure 41/Table 83 (p.130-131): 5.00 x 5.00 x 0.55 mm (D = E 5.00 BSC, A 0.50-0.60); 32 terminals 0.40 x 0.25 mm at the edge on e = 0.50 (L 0.30-0.50, b 0.18-0.30), centres on the footprint pad centres; exposed pad 3.50 x 3.50 mm (D2/E2 3.40-3.60); pin-1 dimple top-left over pad 1 and bottom view pin 1 lower left as Figure 41 (docs/proof/stm32g0b1kbu6-3d-model.png)
  • ✓Pose: stm32g0b1kbu6.step and -etched.step Z-up, seated on z = 0, centred on the pad pattern (offset 0), footprint model binding identity (step_pose.py PASS); MPN etched on the top face with adom-chip-laser 0.2.0; GLBs from step2glb 0.13.2 (glTF-Transform, KHR_mesh_quantization) with PBR materials set by colour
  • •Not modelled: Figure 41's exposed-pad terminal-1 chamfer and corner radii (undimensioned, figure not to scale); terminal thickness A3 (not printed) left at the generator's 0.11 mm
  • ✓DigiKey 497-STM32G0B1KBU6-ND and Mouser 511-STM32G0B1KBU6 confirmed as STM32G0B1KBU6 by STMicroelectronics (2026-10-27)
  • ✓Symbol Datasheet / MPN / Manufacturer / DigiKey / Mouser / LCSC properties agree with page.json; footprint Datasheet property points at the manufacturer datasheet URL
  • ✓component-page-verify: all checks pass; adom-lbr validate OK
Evidencedatasheet (STMicroelectronics, DS13560 Rev 6)3D model views vs Figure 413D model provenance
Verified files✓ stm32g0b1kbu6.kicad_sym✓ stm32g0b1kbu6.kicad_mod✓ stm32g0b1kbu6.step
16 Oct 2026Claude (AI build)Datasheet pins not matched to a symbol pin: EPsuperseded
reviewfor all variants
  • •Datasheet pins not matched to a symbol pin: EP
16 Oct 2026Claude (AI build)3D model provenance: extracted from the source board STEP export (designer custom library ...superseded
reviewfor all variants
  • •3D model provenance: extracted from the source board STEP export (designer custom library STM_CDT); the upstream model licence is not stated, so the page licence is NOASSERTION.
16 Oct 2026Claude (AI build)Footprint is the designer custom STM_CDT:STM32G0B1_UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm;...superseded
reviewfor all variants
  • •Footprint is the designer custom STM_CDT:STM32G0B1_UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm; check it against the UFQFPN32 package drawing.
16 Oct 2026Claude (AI build)Symbol pin names changed to the datasheet spelling (Figure 12, GP version): PC14-OSC32_IN,...superseded
reviewfor all variants
  • •Symbol pin names changed to the datasheet spelling (Figure 12, GP version): PC14-OSC32_IN, PC15-OSC32_OUT, VDD/VDDA, VSS/VSSA, PF2-NRST, PA9, PA10, PA11 [PA9], PA12 [PA10], PA14-BOOT0.
16 Oct 2026Claude (AI build)Automated build checks (awaiting human validation)superseded
SymbolFootprint3D modelPinsfor all variants
  • ✓Footprint extracted pad-for-pad from the source board and normalized to the footprint frame (back-side parts un-mirrored)
  • ✓3D model seated z=0 at footprint origin (placement inverse; method centroid-matched to KiCad library models on 59 cases)
  • ✓adom-lbr generate + lint passed
  • ✓33 of 33 pins described from the datasheet (adom-ds2sf, page-cited)
  • •Not yet checked by a person: land pattern vs datasheet, pin-1/orientation, 3D body vs drawing
Evidencedatasheet
Verified files! stm32g0b1kbu6.kicad_sym✓ stm32g0b1kbu6.kicad_mod! stm32g0b1kbu6.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
← Commit history

Publish 0.1.1

Caleb ·fe38c5cf9f ·1d ago ·parent 7b043d1
13 files changed +10646−12461 diff truncated
README.md+40−37docs/hero.pngdocs/proof/stm32g0b1kbu6-3d-model.pngdocs/stm32g0b1kbu6-datasheet.pdfpackage.json+83−66page.json+90−67provenance/3d-model.json+103provenance/tools/build.sh+13provenance/tools/glbmat.py+55provenance/tools/kicad-generator-ds13560.patch+42provenance/tools/ortho.py+39stm32g0b1kbu6-etched.glbstm32g0b1kbu6-etched.step+10181−12291
README.md+40−37
@@ -4,45 +4,45 @@  **STMicroelectronics** · Microcontrollers · UFQFPN-32(5x5) -STM32G0B1KBU6 from STMicroelectronics, in a UFQFPN-32(5x5). Symbol, footprint and 3D model are the ones used on Adom board designs (3D model extracted from the board STEP export, seated in the footprint frame). Pin functions are extracted from the manufacturer datasheet with page references. **Staged for validation: see the open items in the verification log above.**+STM32G0B1KBU6 from STMicroelectronics, in a UFQFPN-32(5x5). Symbol and footprint are the ones used on Adom board designs; the 3D model is generated with KiCad's package generator at the datasheet's UFQFPN32 dimensions (DS13560 Table 83), seated in the footprint frame. Pin functions are extracted from the manufacturer datasheet with page references.  ## Pinout  | Pin | Name | Type | Function | |---|---|---|---|-| 1 | PB9 | bidirectional | General-purpose I/O PB9. 5 V-tolerant, Fm+ I2C capable. Alt-functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. [datasheet p.47] |-| 2 | PC14-OSC32_IN | bidirectional | GPIO PC14 or 32 kHz LSE crystal input (OSC32_IN). 5 V-tolerant; supplied through RTC-domain power switch (limited to ~3 mA when used as GPIO). Alt-function: TIM1_BKIN2. Additional: OSC32_IN, OSC_IN. [datasheet p.47] |-| 3 | PC15-OSC32_OUT | bidirectional | GPIO PC15 or 32 kHz LSE crystal output (OSC32_OUT). 5 V-tolerant; supplied through RTC-domain power switch (limited to ~3 mA). Alt-functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional: OSC32_OUT. [datasheet p.47] |-| 4 | VDD/VDDA | power_in | Combined digital core/digital I/O supply (VDD) and analog supply (VDDA). Operating range 1.7 V to 3.6 V. Decouple with 100 nF ceramic + bulk capacitor to VSS/VSSA. [datasheet p.47] |-| 5 | VSS/VSSA | power_in | Combined digital and analog ground reference (VSS and VSSA tied together). [datasheet p.47] |-| 6 | PF2-NRST | bidirectional | Bidirectional NRST reset pin with embedded weak pull-up (RST), active low. Can be reconfigured as GPIO PF2. Alt-functions when GPIO: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional: NRST. [datasheet p.47] |-| 7 | PA0 | bidirectional | GPIO PA0 with analog-switch feature (FT_a). ADC_IN0, COMP1_INM8. Alt-functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional: TAMP_IN2, WKUP1. [datasheet p.48] |-| 8 | PA1 | bidirectional | GPIO PA1 with analog-switch + switchable diode (FT_ea). ADC_IN1, COMP1_INP2. Alt-functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. [datasheet p.48] |-| 9 | PA2 | bidirectional | GPIO PA2 (FT_a). ADC_IN2, COMP2_INM8, WKUP4, LSCO. Alt-functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. [datasheet p.48] |-| 10 | PA3 | bidirectional | GPIO PA3 (FT_ea). ADC_IN3, COMP2_INP2. Alt-functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. [datasheet p.48] |-| 11 | PA4 | bidirectional | GPIO PA4 (TT_a — 3.6 V tolerant, analog-switch). ADC_IN4, DAC1_OUT1. Alt-functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional (32-pin only): TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.48] |-| 12 | PA5 | bidirectional | GPIO PA5 (TT_ea — 3.6 V tolerant). ADC_IN5, DAC1_OUT2. Alt-functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. [datasheet p.48] |-| 13 | PA6 | bidirectional | GPIO PA6 (FT_ea). ADC_IN6. Alt-functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. [datasheet p.48] |-| 14 | PA7 | bidirectional | GPIO PA7 (FT_a). ADC_IN7. Alt-functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. [datasheet p.48] |-| 15 | PB0 | bidirectional | GPIO PB0 (FT_ea). ADC_IN8, COMP3_INP0. Alt-functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. [datasheet p.49] |-| 16 | PB1 | bidirectional | GPIO PB1 (FT_ea). ADC_IN9, COMP1_INM6. Alt-functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. [datasheet p.49] |-| 17 | PB2 | bidirectional | GPIO PB2 (FT_ea). ADC_IN10, COMP1_INP1, COMP3_INM6. Alt-functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. [datasheet p.49] |-| 18 | PA8 | bidirectional | GPIO PA8 (FT_fcs — 5 V, Fm+, USB-C PD capable, VDDIO2-selectable). Additional UCPD1_CC1. Alt-functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. [datasheet p.51] |-| 19 | PA9 | bidirectional | GPIO PA9 (FT_fds — 5 V, Fm+, USB-C Dead-Battery capable). Additional UCPD1_DBCC1. Alt-functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. [datasheet p.51] |-| 20 | PC6 | bidirectional | GPIO PC6 (FT_s — 5 V, VDDIO2-only supplied). Alt-functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. [datasheet p.51] |-| 21 | PA10 | bidirectional | GPIO PA10 (FT_fds). Additional UCPD1_DBCC2. Alt-functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. [datasheet p.51] |-| 22 | PA11 [PA9] | bidirectional | GPIO PA11 (FT_fs) by default; remappable to PA9 via SYSCFG_CFGR1. Carries USB_DM (D-) when USB is enabled. Alt-functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. [datasheet p.51] |-| 23 | PA12 [PA10] | bidirectional | GPIO PA12 (FT_fs) by default; remappable to PA10. Carries USB_DP (D+) when USB is enabled. Alt-functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. [datasheet p.51] |-| 24 | PA13 | bidirectional | GPIO PA13 (FT_es). SWDIO after reset with internal pull-up active. Alt-functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. [datasheet p.52] |-| 25 | PA14-BOOT0 | bidirectional | GPIO PA14 (FT_s) with BOOT0 additional function sampled at reset through internal pull-down. SWCLK after reset. Alt-functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional: BOOT0. [datasheet p.52] |-| 26 | PA15 | bidirectional | GPIO PA15 (FT_s). Alt-functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. [datasheet p.52] |-| 27 | PB3 | bidirectional | GPIO PB3 (FT_a). COMP2_INM6. Alt-functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. [datasheet p.54] |-| 28 | PB4 | bidirectional | GPIO PB4 (FT_a). COMP2_INP0. Alt-functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. [datasheet p.54] |-| 29 | PB5 | bidirectional | GPIO PB5 (FT). Additional WKUP6. Alt-functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. [datasheet p.54] |-| 30 | PB6 | bidirectional | GPIO PB6 (FT_fa — 5 V, Fm+, analog-switch). COMP2_INP1. Alt-functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. [datasheet p.55] |-| 31 | PB7 | bidirectional | GPIO PB7 (FT_fa). COMP2_INM7, PVD_IN. Alt-functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. [datasheet p.55] |-| 32 | PB8 | bidirectional | GPIO PB8 (FT_f — 5 V, Fm+ capable). Alt-functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. [datasheet p.55] |-| 33 | VSS | passive | Exposed pad; labelled VSS in the UFQFPN32 GP-version pinout (Figure 12). [datasheet p.45] |+| 1 | PB9 | bidirectional | Port I/O PB9, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. Additional functions: none. [datasheet p.55] |+| 2 | PC14-OSC32_IN | bidirectional | Port I/O PC14-OSC32_IN, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: TIM1_BKIN2. Additional functions: OSC32_IN, OSC_IN. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55] |+| 3 | PC15-OSC32_OUT | bidirectional | Port I/O PC15-OSC32_OUT, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional functions: OSC32_OUT. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55] |+| 4 | VDD/VDDA | power_in | Supply pin (S) [datasheet p.47]. VDD 1.7 V to 3.6 V: external supply for the internal regulator, system analog and the I/Os (VDDIO1 = VDD); the same pin provides VDDA, the analog supply for the ADC, DAC, voltage reference buffer and comparators. On packages without the pin, VBAT is bonded to VDD/VDDA and VREF+ is connected to VDD (keep the voltage reference buffer disabled). [datasheet p.17] |+| 5 | VSS/VSSA | power_in | Supply pin (S): ground, VSS and VSSA on one pin. [datasheet p.47] |+| 6 | PF2-NRST | bidirectional | Port I/O PF2-NRST, I/O structure RST, FT: reset pin with embedded weak pull-up resistor; 5 V tolerant when used as GPIO [datasheet p.46]. Alternate functions: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional functions: NRST. [datasheet p.48] RST I/O structure when configured as reset, FT when configured as GPIO (Table 12 note 3). [datasheet p.55] |+| 7 | PA0 | bidirectional | Port I/O PA0, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional functions: COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1. [datasheet p.48] |+| 8 | PA1 | bidirectional | Port I/O PA1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. Additional functions: COMP1_INP2, ADC_IN1. [datasheet p.48] |+| 9 | PA2 | bidirectional | Port I/O PA2, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. Additional functions: COMP2_INM8, ADC_IN2, WKUP4, LSCO. [datasheet p.48] |+| 10 | PA3 | bidirectional | Port I/O PA3, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. Additional functions: COMP2_INP2, ADC_IN3. [datasheet p.49] |+| 11 | PA4 | bidirectional | Port I/O PA4, I/O structure TT_a: 3.6 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional functions: ADC_IN4, DAC1_OUT1, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.49] |+| 12 | PA5 | bidirectional | Port I/O PA5, I/O structure TT_ea: 3.6 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. Additional functions: ADC_IN5, DAC1_OUT2. [datasheet p.49] |+| 13 | PA6 | bidirectional | Port I/O PA6, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. Additional functions: ADC_IN6. [datasheet p.49] |+| 14 | PA7 | bidirectional | Port I/O PA7, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. Additional functions: ADC_IN7. [datasheet p.49] |+| 15 | PB0 | bidirectional | Port I/O PB0, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. Additional functions: COMP3_INP0, ADC_IN8. [datasheet p.50] |+| 16 | PB1 | bidirectional | Port I/O PB1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. Additional functions: COMP1_INM6, ADC_IN9. [datasheet p.50] |+| 17 | PB2 | bidirectional | Port I/O PB2, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. Additional functions: COMP1_INP1, COMP3_INM6, ADC_IN10. [datasheet p.50] |+| 18 | PA8 | bidirectional | Port I/O PA8, I/O structure FT_fcs: 5 V tolerant, Fm+ capable, USB Type-C PD capable, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. Additional functions: UCPD1_CC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55] |+| 19 | PA9 | bidirectional | Port I/O PA9, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. Additional functions: UCPD1_DBCC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55] |+| 20 | PC6 | bidirectional | Port I/O PC6, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. Additional functions: none. [datasheet p.51] |+| 21 | PA10 | bidirectional | Port I/O PA10, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. Additional functions: UCPD1_DBCC2. [datasheet p.52] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55] |+| 22 | PA11 [PA9] | bidirectional | Port I/O PA11 [PA9], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. Additional functions: USB_DM. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55] |+| 23 | PA12 [PA10] | bidirectional | Port I/O PA12 [PA10], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. Additional functions: USB_DP. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55] |+| 24 | PA13 | bidirectional | Port I/O PA13, I/O structure FT_es: 5 V tolerant, switchable diode to VDDIOx, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. Additional functions: none. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55] |+| 25 | PA14-BOOT0 | bidirectional | Port I/O PA14-BOOT0, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional functions: BOOT0. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55] |+| 26 | PA15 | bidirectional | Port I/O PA15, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. Additional functions: none. [datasheet p.53] |+| 27 | PB3 | bidirectional | Port I/O PB3, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. Additional functions: COMP2_INM6. [datasheet p.54] |+| 28 | PB4 | bidirectional | Port I/O PB4, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. Additional functions: COMP2_INP0. [datasheet p.54] |+| 29 | PB5 | bidirectional | Port I/O PB5, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. Additional functions: WKUP6. [datasheet p.54] |+| 30 | PB6 | bidirectional | Port I/O PB6, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. Additional functions: COMP2_INP1. [datasheet p.55] |+| 31 | PB7 | bidirectional | Port I/O PB7, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. Additional functions: COMP2_INM7, PVD_IN. [datasheet p.55] |+| 32 | PB8 | bidirectional | Port I/O PB8, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. Additional functions: none. [datasheet p.55] |+| 33 | VSS | power_in | Exposed pad, labelled VSS in the UFQFPN32 GP pinout (Figure 4) [datasheet p.37]; 3.50 x 3.50 mm typ (D2, E2 3.40-3.60 mm). [datasheet p.131] |  ## Key specifications @@ -53,6 +53,8 @@ STM32G0B1KBU6 from STMicroelectronics, in a UFQFPN-32(5x5). Symbol, footprint an | Category | Embedded Processors & Controllers | | Pins | 33 | | LCSC | C5159549 |+| Mouser | 511-STM32G0B1KBU6 |+| DigiKey | 497-STM32G0B1KBU6-ND | | Distributor summary (LCSC listing, not datasheet) | -40℃~+85℃ 1.7V~3.6V 128KB 144KB 30 32 Bit 64MHz ARM Cortex-M0+ Built-in+External FLASH UFQFPN-32(5x5) Microcontrollers (MCU/MPU/SOC) ROHS |  ## CAD@@ -60,13 +62,14 @@ STM32G0B1KBU6 from STMicroelectronics, in a UFQFPN-32(5x5). Symbol, footprint an - Symbol: `stm32g0b1kbu6` (source library `MCU_ST_STM32G0:STM32G0B1KBUx`) - Footprint: `STM_CDT:STM32G0B1_UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm` - 3D model path in footprint: `${KIPRJMOD}/stm32g0b1kbu6.step`-- 3D files: `stm32g0b1kbu6-etched.step` / `stm32g0b1kbu6-etched.glb` carry the MPN etch as a separate `Adom.LaserEtch` part; `stm32g0b1kbu6.step` / `stm32g0b1kbu6.glb` are the bare model.+- 3D files: `stm32g0b1kbu6-etched.step` / `stm32g0b1kbu6-etched.glb` carry the MPN etch as a separate `Adom.LaserEtch` part; `stm32g0b1kbu6.step` / `stm32g0b1kbu6.glb` are the bare model. The model is AI-generated (Claude, for Adom) with KiCad's package generator at ST DS13560 Rev 6 Table 83 values (5.00 x 5.00 x 0.55 mm, EP 3.50 x 3.50 mm, L 0.40, b 0.25); it is not ST's CAD and the etched MPN is a virtual mark. Build recipe and source record: `provenance/3d-model.json`, `provenance/tools/`; views against Figure 41: `docs/proof/stm32g0b1kbu6-3d-model.png`. - EAGLE/Fusion library: `stm32g0b1kbu6.lbr` (adom-lbr)  ## Provenance -- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834535048413184) (sha256 `19ad77934ee0849d`, retrieved 2026-10-16, tier: lcsc)-- **CAD:** Footprint, symbol and 3D model as used on Adom board designs; the 3D model was extracted from the board STEP export.+- **Datasheet:** [STMicroelectronics STM32G0B1xB/xC/xE datasheet (DS13560)](https://www.st.com/resource/en/datasheet/stm32g0b1kb.pdf) (DS13560 Rev 6, February 2026, sha256 `8433e47bc5da5cac`, retrieved 2026-10-27, tier: mfr)+- **CAD:** Footprint and symbol as used on Adom board designs; 3D model Adom-generated with the KiCad generator from ST DS13560 Rev 6 Table 83 (p.131).+- **License:** CC-BY-SA-4.0 (Adom content, including the 3D model). - **Pins:** KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7).  [Datasheet PDF](docs/stm32g0b1kbu6-datasheet.pdf)
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package.json+83−66
@@ -1,13 +1,12 @@ {   "slug": "stm32g0b1kbu6",-  "version": "0.1.0",+  "version": "0.1.1",   "type": "component",   "tags": [     "component",     "embedded processors & controllers",     "stm32g0b1kbu6",-    "board-derived",-    "staged-for-validation"+    "board-derived"   ],   "dependencies": {},   "hero": {@@ -27,8 +26,14 @@     "stm32g0b1kbu6.lbr",     "docs/hero.png",     "docs/stm32g0b1kbu6-datasheet.pdf",-    "viewers/symbol.html",-    "viewers/footprint.html"+    "provenance/3d-model.json",+    "provenance/tools/build.sh",+    "provenance/tools/kicad-generator-ds13560.patch",+    "provenance/tools/glbmat.py",+    "provenance/tools/ortho.py",+    "docs/proof/stm32g0b1kbu6-3d-model.png",+    "stm32g0b1kbu6-hero.glb",+    "stm32g0b1kbu6-hero.overlay.json"   ],   "component": {     "mpn": "STM32G0B1KBU6",@@ -37,12 +42,12 @@     "pin_count": 33,     "category": "Embedded Processors & Controllers",     "subcategory": "Microcontrollers",-    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834535048413184",+    "datasheet": "https://www.st.com/resource/en/datasheet/stm32g0b1kb.pdf",     "parts": {       "symbol": "stm32g0b1kbu6.kicad_sym",       "footprint": "stm32g0b1kbu6.kicad_mod",-      "model_3d": "stm32g0b1kbu6-etched.glb",-      "model_3d_plain": "stm32g0b1kbu6.glb",+      "model_3d": "stm32g0b1kbu6-hero.glb",+      "model_3d_plain": "stm32g0b1kbu6-etched.glb",       "model_3d_step": "stm32g0b1kbu6-etched.step",       "model_3d_step_plain": "stm32g0b1kbu6.step",       "lbr": "stm32g0b1kbu6.lbr"@@ -66,199 +71,199 @@         "number": "1",         "name": "PB9",         "type": "bidirectional",-        "description": "General-purpose I/O PB9. 5 V-tolerant, Fm+ I2C capable. Alt-functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. [datasheet p.47]"+        "description": "Port I/O PB9, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. Additional functions: none. [datasheet p.55]"       },       {         "number": "2",         "name": "PC14-OSC32_IN",         "type": "bidirectional",-        "description": "GPIO PC14 or 32 kHz LSE crystal input (OSC32_IN). 5 V-tolerant; supplied through RTC-domain power switch (limited to ~3 mA when used as GPIO). Alt-function: TIM1_BKIN2. Additional: OSC32_IN, OSC_IN. [datasheet p.47]"+        "description": "Port I/O PC14-OSC32_IN, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: TIM1_BKIN2. Additional functions: OSC32_IN, OSC_IN. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55]"       },       {         "number": "3",         "name": "PC15-OSC32_OUT",         "type": "bidirectional",-        "description": "GPIO PC15 or 32 kHz LSE crystal output (OSC32_OUT). 5 V-tolerant; supplied through RTC-domain power switch (limited to ~3 mA). Alt-functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional: OSC32_OUT. [datasheet p.47]"+        "description": "Port I/O PC15-OSC32_OUT, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional functions: OSC32_OUT. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55]"       },       {         "number": "4",         "name": "VDD/VDDA",         "type": "power_in",-        "description": "Combined digital core/digital I/O supply (VDD) and analog supply (VDDA). Operating range 1.7 V to 3.6 V. Decouple with 100 nF ceramic + bulk capacitor to VSS/VSSA. [datasheet p.47]"+        "description": "Supply pin (S) [datasheet p.47]. VDD 1.7 V to 3.6 V: external supply for the internal regulator, system analog and the I/Os (VDDIO1 = VDD); the same pin provides VDDA, the analog supply for the ADC, DAC, voltage reference buffer and comparators. On packages without the pin, VBAT is bonded to VDD/VDDA and VREF+ is connected to VDD (keep the voltage reference buffer disabled). [datasheet p.17]"       },       {         "number": "5",         "name": "VSS/VSSA",         "type": "power_in",-        "description": "Combined digital and analog ground reference (VSS and VSSA tied together). [datasheet p.47]"+        "description": "Supply pin (S): ground, VSS and VSSA on one pin. [datasheet p.47]"       },       {         "number": "6",         "name": "PF2-NRST",         "type": "bidirectional",-        "description": "Bidirectional NRST reset pin with embedded weak pull-up (RST), active low. Can be reconfigured as GPIO PF2. Alt-functions when GPIO: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional: NRST. [datasheet p.47]"+        "description": "Port I/O PF2-NRST, I/O structure RST, FT: reset pin with embedded weak pull-up resistor; 5 V tolerant when used as GPIO [datasheet p.46]. Alternate functions: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional functions: NRST. [datasheet p.48] RST I/O structure when configured as reset, FT when configured as GPIO (Table 12 note 3). [datasheet p.55]"       },       {         "number": "7",         "name": "PA0",         "type": "bidirectional",-        "description": "GPIO PA0 with analog-switch feature (FT_a). ADC_IN0, COMP1_INM8. Alt-functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional: TAMP_IN2, WKUP1. [datasheet p.48]"+        "description": "Port I/O PA0, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional functions: COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1. [datasheet p.48]"       },       {         "number": "8",         "name": "PA1",         "type": "bidirectional",-        "description": "GPIO PA1 with analog-switch + switchable diode (FT_ea). ADC_IN1, COMP1_INP2. Alt-functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. [datasheet p.48]"+        "description": "Port I/O PA1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. Additional functions: COMP1_INP2, ADC_IN1. [datasheet p.48]"       },       {         "number": "9",         "name": "PA2",         "type": "bidirectional",-        "description": "GPIO PA2 (FT_a). ADC_IN2, COMP2_INM8, WKUP4, LSCO. Alt-functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. [datasheet p.48]"+        "description": "Port I/O PA2, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. Additional functions: COMP2_INM8, ADC_IN2, WKUP4, LSCO. [datasheet p.48]"       },       {         "number": "10",         "name": "PA3",         "type": "bidirectional",-        "description": "GPIO PA3 (FT_ea). ADC_IN3, COMP2_INP2. Alt-functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. [datasheet p.48]"+        "description": "Port I/O PA3, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. Additional functions: COMP2_INP2, ADC_IN3. [datasheet p.49]"       },       {         "number": "11",         "name": "PA4",         "type": "bidirectional",-        "description": "GPIO PA4 (TT_a — 3.6 V tolerant, analog-switch). ADC_IN4, DAC1_OUT1. Alt-functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional (32-pin only): TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.48]"+        "description": "Port I/O PA4, I/O structure TT_a: 3.6 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional functions: ADC_IN4, DAC1_OUT1, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.49]"       },       {         "number": "12",         "name": "PA5",         "type": "bidirectional",-        "description": "GPIO PA5 (TT_ea — 3.6 V tolerant). ADC_IN5, DAC1_OUT2. Alt-functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. [datasheet p.48]"+        "description": "Port I/O PA5, I/O structure TT_ea: 3.6 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. Additional functions: ADC_IN5, DAC1_OUT2. [datasheet p.49]"       },       {         "number": "13",         "name": "PA6",         "type": "bidirectional",-        "description": "GPIO PA6 (FT_ea). ADC_IN6. Alt-functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. [datasheet p.48]"+        "description": "Port I/O PA6, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. Additional functions: ADC_IN6. [datasheet p.49]"       },       {         "number": "14",         "name": "PA7",         "type": "bidirectional",-        "description": "GPIO PA7 (FT_a). ADC_IN7. Alt-functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. [datasheet p.48]"+        "description": "Port I/O PA7, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. Additional functions: ADC_IN7. [datasheet p.49]"       },       {         "number": "15",         "name": "PB0",         "type": "bidirectional",-        "description": "GPIO PB0 (FT_ea). ADC_IN8, COMP3_INP0. Alt-functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. [datasheet p.49]"+        "description": "Port I/O PB0, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. Additional functions: COMP3_INP0, ADC_IN8. [datasheet p.50]"       },       {         "number": "16",         "name": "PB1",         "type": "bidirectional",-        "description": "GPIO PB1 (FT_ea). ADC_IN9, COMP1_INM6. Alt-functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. [datasheet p.49]"+        "description": "Port I/O PB1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. Additional functions: COMP1_INM6, ADC_IN9. [datasheet p.50]"       },       {         "number": "17",         "name": "PB2",         "type": "bidirectional",-        "description": "GPIO PB2 (FT_ea). ADC_IN10, COMP1_INP1, COMP3_INM6. Alt-functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. [datasheet p.49]"+        "description": "Port I/O PB2, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. Additional functions: COMP1_INP1, COMP3_INM6, ADC_IN10. [datasheet p.50]"       },       {         "number": "18",         "name": "PA8",         "type": "bidirectional",-        "description": "GPIO PA8 (FT_fcs — 5 V, Fm+, USB-C PD capable, VDDIO2-selectable). Additional UCPD1_CC1. Alt-functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. [datasheet p.51]"+        "description": "Port I/O PA8, I/O structure FT_fcs: 5 V tolerant, Fm+ capable, USB Type-C PD capable, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. Additional functions: UCPD1_CC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"       },       {         "number": "19",         "name": "PA9",         "type": "bidirectional",-        "description": "GPIO PA9 (FT_fds — 5 V, Fm+, USB-C Dead-Battery capable). Additional UCPD1_DBCC1. Alt-functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. [datasheet p.51]"+        "description": "Port I/O PA9, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. Additional functions: UCPD1_DBCC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"       },       {         "number": "20",         "name": "PC6",         "type": "bidirectional",-        "description": "GPIO PC6 (FT_s — 5 V, VDDIO2-only supplied). Alt-functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. [datasheet p.51]"+        "description": "Port I/O PC6, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. Additional functions: none. [datasheet p.51]"       },       {         "number": "21",         "name": "PA10",         "type": "bidirectional",-        "description": "GPIO PA10 (FT_fds). Additional UCPD1_DBCC2. Alt-functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. [datasheet p.51]"+        "description": "Port I/O PA10, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. Additional functions: UCPD1_DBCC2. [datasheet p.52] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"       },       {         "number": "22",         "name": "PA11 [PA9]",         "type": "bidirectional",-        "description": "GPIO PA11 (FT_fs) by default; remappable to PA9 via SYSCFG_CFGR1. Carries USB_DM (D-) when USB is enabled. Alt-functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. [datasheet p.51]"+        "description": "Port I/O PA11 [PA9], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. Additional functions: USB_DM. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55]"       },       {         "number": "23",         "name": "PA12 [PA10]",         "type": "bidirectional",-        "description": "GPIO PA12 (FT_fs) by default; remappable to PA10. Carries USB_DP (D+) when USB is enabled. Alt-functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. [datasheet p.51]"+        "description": "Port I/O PA12 [PA10], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. Additional functions: USB_DP. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55]"       },       {         "number": "24",         "name": "PA13",         "type": "bidirectional",-        "description": "GPIO PA13 (FT_es). SWDIO after reset with internal pull-up active. Alt-functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. [datasheet p.52]"+        "description": "Port I/O PA13, I/O structure FT_es: 5 V tolerant, switchable diode to VDDIOx, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. Additional functions: none. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55]"       },       {         "number": "25",         "name": "PA14-BOOT0",         "type": "bidirectional",-        "description": "GPIO PA14 (FT_s) with BOOT0 additional function sampled at reset through internal pull-down. SWCLK after reset. Alt-functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional: BOOT0. [datasheet p.52]"+        "description": "Port I/O PA14-BOOT0, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional functions: BOOT0. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55]"       },       {         "number": "26",         "name": "PA15",         "type": "bidirectional",-        "description": "GPIO PA15 (FT_s). Alt-functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. [datasheet p.52]"+        "description": "Port I/O PA15, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. Additional functions: none. [datasheet p.53]"       },       {         "number": "27",         "name": "PB3",         "type": "bidirectional",-        "description": "GPIO PB3 (FT_a). COMP2_INM6. Alt-functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. [datasheet p.54]"+        "description": "Port I/O PB3, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. Additional functions: COMP2_INM6. [datasheet p.54]"       },       {         "number": "28",         "name": "PB4",         "type": "bidirectional",-        "description": "GPIO PB4 (FT_a). COMP2_INP0. Alt-functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. [datasheet p.54]"+        "description": "Port I/O PB4, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. Additional functions: COMP2_INP0. [datasheet p.54]"       },       {         "number": "29",         "name": "PB5",         "type": "bidirectional",-        "description": "GPIO PB5 (FT). Additional WKUP6. Alt-functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. [datasheet p.54]"+        "description": "Port I/O PB5, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. Additional functions: WKUP6. [datasheet p.54]"       },       {         "number": "30",         "name": "PB6",         "type": "bidirectional",-        "description": "GPIO PB6 (FT_fa — 5 V, Fm+, analog-switch). COMP2_INP1. Alt-functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. [datasheet p.55]"+        "description": "Port I/O PB6, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. Additional functions: COMP2_INP1. [datasheet p.55]"       },       {         "number": "31",         "name": "PB7",         "type": "bidirectional",-        "description": "GPIO PB7 (FT_fa). COMP2_INM7, PVD_IN. Alt-functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. [datasheet p.55]"+        "description": "Port I/O PB7, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. Additional functions: COMP2_INM7, PVD_IN. [datasheet p.55]"       },       {         "number": "32",         "name": "PB8",         "type": "bidirectional",-        "description": "GPIO PB8 (FT_f — 5 V, Fm+ capable). Alt-functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. [datasheet p.55]"+        "description": "Port I/O PB8, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. Additional functions: none. [datasheet p.55]"       },       {         "number": "33",         "name": "VSS",-        "type": "passive",-        "description": "Exposed pad; labelled VSS in the UFQFPN32 GP-version pinout (Figure 12). [datasheet p.45]"+        "type": "power_in",+        "description": "Exposed pad, labelled VSS in the UFQFPN32 GP pinout (Figure 4) [datasheet p.37]; 3.50 x 3.50 mm typ (D2, E2 3.40-3.60 mm). [datasheet p.131]"       }     ],     "provenance": {@@ -268,12 +273,14 @@         "at": "2026-10-16"       },       "datasheet": {-        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834535048413184",-        "pages": 159,-        "sha256": "19ad77934ee0849dbf613999149675086b13912adbafca09b8c37b8bfa76b053",-        "source_tier": "lcsc"-      },-      "cad": "Footprint, symbol and 3D model as used on Adom board designs; the 3D model was extracted from the board STEP export",+        "url": "https://www.st.com/resource/en/datasheet/stm32g0b1kb.pdf",+        "pages": 165,+        "sha256": "8433e47bc5da5cac459a1d3d5a6add183655061f5655d3c653248de65ca535c9",+        "source_tier": "mfr",+        "retrieved": "2026-10-27",+        "edition": "DS13560 Rev 6, February 2026"+      },+      "cad": "3D model Adom-generated with KiCad's package generator (kicad-footprint-generator package/no_lead) at ST DS13560 Rev 6 Table 83 UFQFPN32 values (tier 3; no redistributable ST or KiCad-library model fits), CC-BY-SA-4.0; footprint and symbol as used on Adom board designs",       "pins": {         "total": 33,         "described": 33,@@ -281,48 +288,58 @@         "refuses_to_fabricate": true       }     },-    "viewers": {-      "symbol": "viewers/symbol.html",-      "footprint": "viewers/footprint.html"-    },     "models_3d": [       {         "file": "stm32g0b1kbu6.step",         "role": "plain",         "up": "Z",         "units": "mm",-        "origin": "footprint origin",-        "seat": "z = 0 (PCB top surface)",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",         "extents_mm": [           5.0,           5.0,           0.55         ],-        "zmin_mm": -0.0,+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,         "footprint_binding": "identity",-        "sha256": "d78e7cbde5c638c998f2a03f4a479341b393764138cdd65a74485c919619a77d",-        "checked": "2026-10-16",-        "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+        "sha256": "7ae4d90a64b22c011b9b2b25658a7d45899f4c08b3d76d262cd7eb702c6f38bb",+        "checked": "2026-10-27",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)",+        "source": {+          "manufacturer": "STMicroelectronics (drawing only)",+          "file": "stm32g0b1kbu6.step",+          "kind": "generated",+          "generator": "KiCad library 3D generator (kicad-footprint-generator 6ef68694, package/no_lead) at ST DS13560 Rev 6 Table 83 values",+          "source_page": "https://www.st.com/en/microcontrollers-microprocessors/stm32g0b1kb.html",+          "download": "none: ST CAD only via SamacSys / Ultra Librarian behind my.st.com login or e-mail validation (checked 2026-10-27/28)",+          "colour": "KiCad generator colours (black body, metal grey pins)",+          "retrieved": "2026-10-27",+          "posed_by": "generated in the footprint frame (identity); provenance/3d-model.json",+          "sha256": "7ae4d90a64b22c011b9b2b25658a7d45899f4c08b3d76d262cd7eb702c6f38bb"+        }       },       {         "file": "stm32g0b1kbu6-etched.step",         "role": "eda",         "up": "Z",         "units": "mm",-        "origin": "footprint origin",-        "seat": "z = 0 (PCB top surface)",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",         "extents_mm": [           5.0,           5.0,-          0.552+          0.55         ],-        "zmin_mm": -0.0,+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,         "footprint_binding": "identity",-        "sha256": "a81d15c854269feed566681fcca9c14d064d445d8b32ba2a9f15aa1a746881fe",-        "checked": "2026-10-16",-        "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+        "sha256": "eefc133a0abc9d1da06cb2da0d77190b2f8036fa0381321917761e8a6dc9baf8",+        "checked": "2026-10-27",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }     ]   },   "description": "STMicroelectronics Microcontrollers, UFQFPN-32(5x5). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet."-}\ No newline at end of file+}
page.json+90−67
@@ -4,14 +4,13 @@   "slug": "stm32g0b1kbu6",   "title": "STM32G0B1KBU6",   "brief": "STMicroelectronics Microcontrollers, UFQFPN-32(5x5). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.",-  "version": "0.1.0",+  "version": "0.1.1",   "license": "NOASSERTION",   "tags": [     "component",     "embedded processors & controllers",     "stm32g0b1kbu6",-    "board-derived",-    "staged-for-validation"+    "board-derived"   ],   "component": {     "mpn": "STM32G0B1KBU6",@@ -20,12 +19,12 @@     "pin_count": 33,     "category": "Embedded Processors & Controllers",     "subcategory": "Microcontrollers",-    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834535048413184",+    "datasheet": "https://www.st.com/resource/en/datasheet/stm32g0b1kb.pdf",     "parts": {       "symbol": "stm32g0b1kbu6.kicad_sym",       "footprint": "stm32g0b1kbu6.kicad_mod",-      "model_3d": "stm32g0b1kbu6-etched.glb",-      "model_3d_plain": "stm32g0b1kbu6.glb",+      "model_3d": "stm32g0b1kbu6-hero.glb",+      "model_3d_plain": "stm32g0b1kbu6-etched.glb",       "model_3d_step": "stm32g0b1kbu6-etched.step",       "model_3d_step_plain": "stm32g0b1kbu6.step",       "lbr": "stm32g0b1kbu6.lbr"@@ -49,199 +48,199 @@         "number": "1",         "name": "PB9",         "type": "bidirectional",-        "description": "General-purpose I/O PB9. 5 V-tolerant, Fm+ I2C capable. Alt-functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. [datasheet p.47]"+        "description": "Port I/O PB9, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. Additional functions: none. [datasheet p.55]"       },       {         "number": "2",         "name": "PC14-OSC32_IN",         "type": "bidirectional",-        "description": "GPIO PC14 or 32 kHz LSE crystal input (OSC32_IN). 5 V-tolerant; supplied through RTC-domain power switch (limited to ~3 mA when used as GPIO). Alt-function: TIM1_BKIN2. Additional: OSC32_IN, OSC_IN. [datasheet p.47]"+        "description": "Port I/O PC14-OSC32_IN, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: TIM1_BKIN2. Additional functions: OSC32_IN, OSC_IN. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55]"       },       {         "number": "3",         "name": "PC15-OSC32_OUT",         "type": "bidirectional",-        "description": "GPIO PC15 or 32 kHz LSE crystal output (OSC32_OUT). 5 V-tolerant; supplied through RTC-domain power switch (limited to ~3 mA). Alt-functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional: OSC32_OUT. [datasheet p.47]"+        "description": "Port I/O PC15-OSC32_OUT, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional functions: OSC32_OUT. [datasheet p.47] Supplied through the power switch (3 mA): as an output it is limited to 2 MHz with 30 pF and can sink but not source current; after an RTC domain power-up it operates as a GPIO whose function then depends on the RTC registers, which system reset does not reset (Table 12 notes 1-2). [datasheet p.55]"       },       {         "number": "4",         "name": "VDD/VDDA",         "type": "power_in",-        "description": "Combined digital core/digital I/O supply (VDD) and analog supply (VDDA). Operating range 1.7 V to 3.6 V. Decouple with 100 nF ceramic + bulk capacitor to VSS/VSSA. [datasheet p.47]"+        "description": "Supply pin (S) [datasheet p.47]. VDD 1.7 V to 3.6 V: external supply for the internal regulator, system analog and the I/Os (VDDIO1 = VDD); the same pin provides VDDA, the analog supply for the ADC, DAC, voltage reference buffer and comparators. On packages without the pin, VBAT is bonded to VDD/VDDA and VREF+ is connected to VDD (keep the voltage reference buffer disabled). [datasheet p.17]"       },       {         "number": "5",         "name": "VSS/VSSA",         "type": "power_in",-        "description": "Combined digital and analog ground reference (VSS and VSSA tied together). [datasheet p.47]"+        "description": "Supply pin (S): ground, VSS and VSSA on one pin. [datasheet p.47]"       },       {         "number": "6",         "name": "PF2-NRST",         "type": "bidirectional",-        "description": "Bidirectional NRST reset pin with embedded weak pull-up (RST), active low. Can be reconfigured as GPIO PF2. Alt-functions when GPIO: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional: NRST. [datasheet p.47]"+        "description": "Port I/O PF2-NRST, I/O structure RST, FT: reset pin with embedded weak pull-up resistor; 5 V tolerant when used as GPIO [datasheet p.46]. Alternate functions: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional functions: NRST. [datasheet p.48] RST I/O structure when configured as reset, FT when configured as GPIO (Table 12 note 3). [datasheet p.55]"       },       {         "number": "7",         "name": "PA0",         "type": "bidirectional",-        "description": "GPIO PA0 with analog-switch feature (FT_a). ADC_IN0, COMP1_INM8. Alt-functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional: TAMP_IN2, WKUP1. [datasheet p.48]"+        "description": "Port I/O PA0, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional functions: COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1. [datasheet p.48]"       },       {         "number": "8",         "name": "PA1",         "type": "bidirectional",-        "description": "GPIO PA1 with analog-switch + switchable diode (FT_ea). ADC_IN1, COMP1_INP2. Alt-functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. [datasheet p.48]"+        "description": "Port I/O PA1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. Additional functions: COMP1_INP2, ADC_IN1. [datasheet p.48]"       },       {         "number": "9",         "name": "PA2",         "type": "bidirectional",-        "description": "GPIO PA2 (FT_a). ADC_IN2, COMP2_INM8, WKUP4, LSCO. Alt-functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. [datasheet p.48]"+        "description": "Port I/O PA2, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. Additional functions: COMP2_INM8, ADC_IN2, WKUP4, LSCO. [datasheet p.48]"       },       {         "number": "10",         "name": "PA3",         "type": "bidirectional",-        "description": "GPIO PA3 (FT_ea). ADC_IN3, COMP2_INP2. Alt-functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. [datasheet p.48]"+        "description": "Port I/O PA3, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. Additional functions: COMP2_INP2, ADC_IN3. [datasheet p.49]"       },       {         "number": "11",         "name": "PA4",         "type": "bidirectional",-        "description": "GPIO PA4 (TT_a — 3.6 V tolerant, analog-switch). ADC_IN4, DAC1_OUT1. Alt-functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional (32-pin only): TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.48]"+        "description": "Port I/O PA4, I/O structure TT_a: 3.6 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional functions: ADC_IN4, DAC1_OUT1, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.49]"       },       {         "number": "12",         "name": "PA5",         "type": "bidirectional",-        "description": "GPIO PA5 (TT_ea — 3.6 V tolerant). ADC_IN5, DAC1_OUT2. Alt-functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. [datasheet p.48]"+        "description": "Port I/O PA5, I/O structure TT_ea: 3.6 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. Additional functions: ADC_IN5, DAC1_OUT2. [datasheet p.49]"       },       {         "number": "13",         "name": "PA6",         "type": "bidirectional",-        "description": "GPIO PA6 (FT_ea). ADC_IN6. Alt-functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. [datasheet p.48]"+        "description": "Port I/O PA6, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. Additional functions: ADC_IN6. [datasheet p.49]"       },       {         "number": "14",         "name": "PA7",         "type": "bidirectional",-        "description": "GPIO PA7 (FT_a). ADC_IN7. Alt-functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. [datasheet p.48]"+        "description": "Port I/O PA7, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. Additional functions: ADC_IN7. [datasheet p.49]"       },       {         "number": "15",         "name": "PB0",         "type": "bidirectional",-        "description": "GPIO PB0 (FT_ea). ADC_IN8, COMP3_INP0. Alt-functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. [datasheet p.49]"+        "description": "Port I/O PB0, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. Additional functions: COMP3_INP0, ADC_IN8. [datasheet p.50]"       },       {         "number": "16",         "name": "PB1",         "type": "bidirectional",-        "description": "GPIO PB1 (FT_ea). ADC_IN9, COMP1_INM6. Alt-functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. [datasheet p.49]"+        "description": "Port I/O PB1, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. Additional functions: COMP1_INM6, ADC_IN9. [datasheet p.50]"       },       {         "number": "17",         "name": "PB2",         "type": "bidirectional",-        "description": "GPIO PB2 (FT_ea). ADC_IN10, COMP1_INP1, COMP3_INM6. Alt-functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. [datasheet p.49]"+        "description": "Port I/O PB2, I/O structure FT_ea: 5 V tolerant, switchable diode to VDDIOx, analog switch function [datasheet p.46]. Alternate functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. Additional functions: COMP1_INP1, COMP3_INM6, ADC_IN10. [datasheet p.50]"       },       {         "number": "18",         "name": "PA8",         "type": "bidirectional",-        "description": "GPIO PA8 (FT_fcs — 5 V, Fm+, USB-C PD capable, VDDIO2-selectable). Additional UCPD1_CC1. Alt-functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. [datasheet p.51]"+        "description": "Port I/O PA8, I/O structure FT_fcs: 5 V tolerant, Fm+ capable, USB Type-C PD capable, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. Additional functions: UCPD1_CC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"       },       {         "number": "19",         "name": "PA9",         "type": "bidirectional",-        "description": "GPIO PA9 (FT_fds — 5 V, Fm+, USB-C Dead-Battery capable). Additional UCPD1_DBCC1. Alt-functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. [datasheet p.51]"+        "description": "Port I/O PA9, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. Additional functions: UCPD1_DBCC1. [datasheet p.51] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"       },       {         "number": "20",         "name": "PC6",         "type": "bidirectional",-        "description": "GPIO PC6 (FT_s — 5 V, VDDIO2-only supplied). Alt-functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. [datasheet p.51]"+        "description": "Port I/O PC6, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. Additional functions: none. [datasheet p.51]"       },       {         "number": "21",         "name": "PA10",         "type": "bidirectional",-        "description": "GPIO PA10 (FT_fds). Additional UCPD1_DBCC2. Alt-functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. [datasheet p.51]"+        "description": "Port I/O PA10, I/O structure FT_fds: 5 V tolerant, Fm+ capable, USB Type-C PD Dead Battery function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. Additional functions: UCPD1_DBCC2. [datasheet p.52] Table 12 note 4: upon reset a pull-down might be present on PA8, PB15, PD0 or PD2 depending on the voltage on PA9, PA10, PD1 and PD3 respectively; strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 at start-up to disable it. [datasheet p.55]"       },       {         "number": "22",         "name": "PA11 [PA9]",         "type": "bidirectional",-        "description": "GPIO PA11 (FT_fs) by default; remappable to PA9 via SYSCFG_CFGR1. Carries USB_DM (D-) when USB is enabled. Alt-functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. [datasheet p.51]"+        "description": "Port I/O PA11 [PA9], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. Additional functions: USB_DM. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55]"       },       {         "number": "23",         "name": "PA12 [PA10]",         "type": "bidirectional",-        "description": "GPIO PA12 (FT_fs) by default; remappable to PA10. Carries USB_DP (D+) when USB is enabled. Alt-functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. [datasheet p.51]"+        "description": "Port I/O PA12 [PA10], I/O structure FT_fus: 5 V tolerant, Fm+ capable, USB function, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. Additional functions: USB_DP. [datasheet p.52] PA9/PA10 can be remapped in place of PA11/PA12 (default mapping) using SYSCFG_CFGR1 (Table 12 note 5). [datasheet p.55]"       },       {         "number": "24",         "name": "PA13",         "type": "bidirectional",-        "description": "GPIO PA13 (FT_es). SWDIO after reset with internal pull-up active. Alt-functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. [datasheet p.52]"+        "description": "Port I/O PA13, I/O structure FT_es: 5 V tolerant, switchable diode to VDDIOx, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. Additional functions: none. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55]"       },       {         "number": "25",         "name": "PA14-BOOT0",         "type": "bidirectional",-        "description": "GPIO PA14 (FT_s) with BOOT0 additional function sampled at reset through internal pull-down. SWCLK after reset. Alt-functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional: BOOT0. [datasheet p.52]"+        "description": "Port I/O PA14-BOOT0, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional functions: BOOT0. [datasheet p.53] Upon reset configured as SW debug alternate function, with the internal pull-up on PA13 and pull-down on PA14 active (Table 12 note 6). [datasheet p.55]"       },       {         "number": "26",         "name": "PA15",         "type": "bidirectional",-        "description": "GPIO PA15 (FT_s). Alt-functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. [datasheet p.52]"+        "description": "Port I/O PA15, I/O structure FT_s: 5 V tolerant, supplied from VDDIO2 only [datasheet p.46]; VDDIO2 is connected internally to VDD on packages without a VDDIO2 pin [datasheet p.17]. Alternate functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. Additional functions: none. [datasheet p.53]"       },       {         "number": "27",         "name": "PB3",         "type": "bidirectional",-        "description": "GPIO PB3 (FT_a). COMP2_INM6. Alt-functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. [datasheet p.54]"+        "description": "Port I/O PB3, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. Additional functions: COMP2_INM6. [datasheet p.54]"       },       {         "number": "28",         "name": "PB4",         "type": "bidirectional",-        "description": "GPIO PB4 (FT_a). COMP2_INP0. Alt-functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. [datasheet p.54]"+        "description": "Port I/O PB4, I/O structure FT_a: 5 V tolerant, analog switch function [datasheet p.46]. Alternate functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. Additional functions: COMP2_INP0. [datasheet p.54]"       },       {         "number": "29",         "name": "PB5",         "type": "bidirectional",-        "description": "GPIO PB5 (FT). Additional WKUP6. Alt-functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. [datasheet p.54]"+        "description": "Port I/O PB5, I/O structure FT: 5 V tolerant [datasheet p.46]. Alternate functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. Additional functions: WKUP6. [datasheet p.54]"       },       {         "number": "30",         "name": "PB6",         "type": "bidirectional",-        "description": "GPIO PB6 (FT_fa — 5 V, Fm+, analog-switch). COMP2_INP1. Alt-functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. [datasheet p.55]"+        "description": "Port I/O PB6, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. Additional functions: COMP2_INP1. [datasheet p.55]"       },       {         "number": "31",         "name": "PB7",         "type": "bidirectional",-        "description": "GPIO PB7 (FT_fa). COMP2_INM7, PVD_IN. Alt-functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. [datasheet p.55]"+        "description": "Port I/O PB7, I/O structure FT_fa: 5 V tolerant, Fm+ capable, analog switch function [datasheet p.46]. Alternate functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. Additional functions: COMP2_INM7, PVD_IN. [datasheet p.55]"       },       {         "number": "32",         "name": "PB8",         "type": "bidirectional",-        "description": "GPIO PB8 (FT_f — 5 V, Fm+ capable). Alt-functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. [datasheet p.55]"+        "description": "Port I/O PB8, I/O structure FT_f: 5 V tolerant, Fm+ capable [datasheet p.46]. Alternate functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. Additional functions: none. [datasheet p.55]"       },       {         "number": "33",         "name": "VSS",-        "type": "passive",-        "description": "Exposed pad; labelled VSS in the UFQFPN32 GP-version pinout (Figure 12). [datasheet p.45]"+        "type": "power_in",+        "description": "Exposed pad, labelled VSS in the UFQFPN32 GP pinout (Figure 4) [datasheet p.37]; 3.50 x 3.50 mm typ (D2, E2 3.40-3.60 mm). [datasheet p.131]"       }     ],     "provenance": {@@ -251,12 +250,14 @@         "at": "2026-10-16"       },       "datasheet": {-        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834535048413184",-        "pages": 159,-        "sha256": "19ad77934ee0849dbf613999149675086b13912adbafca09b8c37b8bfa76b053",-        "source_tier": "lcsc"-      },-      "cad": "Footprint, symbol and 3D model as used on Adom board designs; the 3D model was extracted from the board STEP export",+        "url": "https://www.st.com/resource/en/datasheet/stm32g0b1kb.pdf",+        "pages": 165,+        "sha256": "8433e47bc5da5cac459a1d3d5a6add183655061f5655d3c653248de65ca535c9",+        "source_tier": "mfr",+        "retrieved": "2026-10-27",+        "edition": "DS13560 Rev 6, February 2026"+      },+      "cad": "3D model Adom-generated with KiCad's package generator (kicad-footprint-generator package/no_lead) at ST DS13560 Rev 6 Table 83 UFQFPN32 values (tier 3; no redistributable ST or KiCad-library model fits), CC-BY-SA-4.0; footprint and symbol as used on Adom board designs",       "pins": {         "total": 33,         "described": 33,@@ -270,36 +271,50 @@         "role": "plain",         "up": "Z",         "units": "mm",-        "origin": "footprint origin",-        "seat": "z = 0 (PCB top surface)",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",         "extents_mm": [-          5.0,-          5.0,+          5,+          5,           0.55         ],-        "zmin_mm": -0.0,+        "zmin_mm": 0,+        "centre_offset_mm": 0,         "footprint_binding": "identity",-        "sha256": "d78e7cbde5c638c998f2a03f4a479341b393764138cdd65a74485c919619a77d",-        "checked": "2026-10-16",-        "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+        "sha256": "7ae4d90a64b22c011b9b2b25658a7d45899f4c08b3d76d262cd7eb702c6f38bb",+        "checked": "2026-10-27",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)",+        "source": {+          "manufacturer": "STMicroelectronics (drawing only)",+          "file": "stm32g0b1kbu6.step",+          "kind": "generated",+          "generator": "KiCad library 3D generator (kicad-footprint-generator 6ef68694, package/no_lead) at ST DS13560 Rev 6 Table 83 values",+          "source_page": "https://www.st.com/en/microcontrollers-microprocessors/stm32g0b1kb.html",+          "download": "none: ST CAD only via SamacSys / Ultra Librarian behind my.st.com login or e-mail validation (checked 2026-10-27/28)",+          "colour": "KiCad generator colours (black body, metal grey pins)",+          "retrieved": "2026-10-27",+          "posed_by": "generated in the footprint frame (identity); provenance/3d-model.json",+          "sha256": "7ae4d90a64b22c011b9b2b25658a7d45899f4c08b3d76d262cd7eb702c6f38bb"+        }       },       {         "file": "stm32g0b1kbu6-etched.step",         "role": "eda",         "up": "Z",         "units": "mm",-        "origin": "footprint origin",-        "seat": "z = 0 (PCB top surface)",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",         "extents_mm": [-          5.0,-          5.0,-          0.552+          5,+          5,+          0.55         ],-        "zmin_mm": -0.0,+        "zmin_mm": 0,+        "centre_offset_mm": 0,         "footprint_binding": "identity",-        "sha256": "a81d15c854269feed566681fcca9c14d064d445d8b32ba2a9f15aa1a746881fe",-        "checked": "2026-10-16",-        "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+        "sha256": "eefc133a0abc9d1da06cb2da0d77190b2f8036fa0381321917761e8a6dc9baf8",+        "checked": "2026-10-27",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }     ]   },@@ -346,9 +361,17 @@     "stm32g0b1kbu6.step",     "stm32g0b1kbu6.lbr",     "docs/hero.png",-    "docs/stm32g0b1kbu6-datasheet.pdf"+    "docs/stm32g0b1kbu6-datasheet.pdf",+    "provenance/3d-model.json",+    "provenance/tools/build.sh",+    "provenance/tools/kicad-generator-ds13560.patch",+    "provenance/tools/glbmat.py",+    "provenance/tools/ortho.py",+    "docs/proof/stm32g0b1kbu6-3d-model.png",+    "stm32g0b1kbu6-hero.glb",+    "stm32g0b1kbu6-hero.overlay.json"   ],-  "visibility": {-    "public": false-  }+  "visibility": "public",+  "description": "STMicroelectronics Microcontrollers, UFQFPN-32(5x5). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.",+  "org": "adom" }\ No newline at end of file
provenance/3d-model.jsonadded+103
@@ -0,0 +1,103 @@+{+ "schema": "adom/3d-model-provenance@1",+ "mpn": "STM32G0B1KBU6",+ "date": "2026-10-27",+ "classification": "Generated (tier 3): KiCad's own package generator run at the datasheet's values by Claude (AI) for Caleb Taylor; not ST CAD and not an ST certification",+ "source": {+  "tier": 3,+  "what": "Adom-generated with the KiCad generator from ST DS13560 Rev 6 (February 2026), Table 83 UFQFPN32 mechanical data (p.131) and Figure 41 outline (p.130)",+  "generator": "gitlab.com/kicad/libraries/kicad-footprint-generator @ 6ef686944ab44b3d3d75965a66730ac65d057e63 (2026-10-05), generator package/no_lead (make_qfn), CadQuery 2.8.0",+  "generator_key": "UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm (KiCad's own spec for ST UFQFPN32, re-valued to DS13560 by provenance/tools/kicad-generator-ds13560.patch)",+  "terms": "CC-BY-SA-4.0 (Adom-authored model; the STEP header carries the KiCad library licence text, CC-BY-SA 4.0 with the KiCad libraries' design exception, which the generator writes). Generator scripts are GPL; their output is not.",+  "generated_sha256": "fc2dacc1d92286491f5368edfe51cd5a3c9d624d1534ea68d1933a6b3ce0184f",+  "header_note": "stm32g0b1kbu6.step is the generator output with the STEP header's author/description/name rewritten to Adom; the DATA section is byte-identical"+ },+ "tiers_tried": [+  {+   "tier": 1,+   "result": "not usable",+   "why": "ST's CAD for STM32G0B1KB is offered only through SamacSys and Ultra Librarian links behind a my.st.com login or e-mail validation (st.com product page CAD Resources, fetched 2026-10-27); a login wall, and those suppliers' terms do not allow redistributing models in a library"+  },+  {+   "tier": 2,+   "result": "not usable",+   "why": "KiCad has no UFQFPN-32 5x5 EP3.5 model in kicad-packages3D (Package_DFN_QFN.3dshapes/UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm.step: 404 on 2026-10-27); the nearest, QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm.step, is 0.77 mm tall against A 0.50-0.60"+  }+ ],+ "values": {+  "D": 5.0,+  "E": 5.0,+  "A": 0.55,+  "A1": 0.0,+  "b": 0.25,+  "e": 0.5,+  "L": 0.4,+  "D2": 3.5,+  "E2": 3.5,+  "N": 32,+  "notes": "A at its typical 0.55 (0.50-0.60), A1 at 0 (0-0.05), b typical 0.25 (0.18-0.30), L 0.40 = midpoint of 0.30-0.50 (no typical printed), D2/E2 typical 3.50 (3.40-3.60). Undimensioned: terminal thickness (A3 not printed) left at the generator's A/5 = 0.11 mm; the generator's rounded terminal inner end (radius b/2 = 0.125, Figure 41 Detail C shows radiused corners R >= 0.09); the exposed pad's terminal-1 chamfer and corner radii in Figure 41 are not dimensioned (the figure is not to scale) and are not modelled; KiCad's 0.5 mm pin-1 dimple on top marks pin 1 (Figure 41 top view: terminal A1 index area)"+ },+ "measured": {+  "extents_mm": [+   5.0,+   5.0,+   0.55+  ],+  "terminals": "32 x 0.400 x 0.250 mm at the body edge, centres +/-1.75..+/-0.25 on 0.50 pitch, matching the footprint pad centres",+  "exposed_pad_mm": [+   3.5,+   3.5+  ],+  "pin1": "dimple at (-2.0, +2.0) mm (top-left, STEP Y up) = footprint pin 1 at (-2.4375, -1.75) KiCad"+ },+ "transform": {+  "source_up": "Z",+  "seat": "z = 0",+  "rotation": "none",+  "translation": "none",+  "origin": "package centre = footprint origin = pad-pattern centre"+ },+ "files": {+  "stm32g0b1kbu6.step": {+   "sha256": "7ae4d90a64b22c011b9b2b25658a7d45899f4c08b3d76d262cd7eb702c6f38bb",+   "role": "plain"+  },+  "stm32g0b1kbu6-etched.step": {+   "sha256": "eefc133a0abc9d1da06cb2da0d77190b2f8036fa0381321917761e8a6dc9baf8",+   "role": "eda",+   "etch": "adom-chip-laser 0.2.0 etch, face top, font 0.558 mm, Adom.LaserEtch part (virtual mark, not ST's marking)"+  },+  "stm32g0b1kbu6.glb": {+   "sha256": "33baba74f821f5c189d711bf637a359de501ca4e8530b29f0aaabfe5840f6e00"+  },+  "stm32g0b1kbu6-etched.glb": {+   "sha256": "d69cf41aaa7a62c0dae6ea9cff4d2349ea6c4c66d4977c696e3bf30b02594ee9"+  },+  "glb_note": "step2glb convert (glTF-Transform v4.4.0, KHR_mesh_quantization, Z-up content in metres), then provenance/tools/glbmat.py sets PBR metallic/roughness by base colour (epoxy body, matte-tin terminals, pin-1 mark, etch)"+ },+ "checks": [+  "step_pose.py plain and eda: PASS (Z-up, zmin 0, centre offset 0, binding identity)",+  "extents 5.00 x 5.00 x 0.55 within D = E 5.00 BSC (aaa 0.15) and A 0.50-0.60",+  "terminal L 0.40 within 0.30-0.50, b 0.25 within 0.18-0.30, EP 3.50 within 3.40-3.60, 32 terminals at e 0.50",+  "bottom view pin 1 at lower left, as Figure 41 (docs/proof/stm32g0b1kbu6-3d-model.png)"+ ],+ "evidence": [+  "docs/proof/stm32g0b1kbu6-3d-model.png"+ ],+ "replaced": {+  "why": "the previous model was extracted from a board STEP export and carried no licence (page licence NOASSERTION); it is not kept in the bundle, the wiki history holds it",+  "files": {+   "stm32g0b1kbu6.step": "d78e7cbde5c638c998f2a03f4a479341b393764138cdd65a74485c919619a77d",+   "stm32g0b1kbu6-etched.step": "a81d15c854269feed566681fcca9c14d064d445d8b32ba2a9f15aa1a746881fe",+   "stm32g0b1kbu6.glb": "bd0baf992960f81faee93c84719478dec8f6f8b1be88d69872b9998722e34086",+   "stm32g0b1kbu6-etched.glb": "3b5ab072fc6353b364abe724ea87500eb1c0944459b9323181e00bd905c1f271"+  }+ },+ "tools": {+  "kicad-footprint-generator": "6ef68694",+  "cadquery": "2.8.0",+  "step2glb": "0.13.2",+  "adom-chip-laser": "0.2.0"+ },+ "license": "CC-BY-SA-4.0"+}\ No newline at end of file
provenance/tools/build.shadded+13
@@ -0,0 +1,13 @@+#!/bin/bash+# Rebuild the STM32G0B1KBU6 3D model (Adom, 2026-10-27). Needs cadquery 2.8, step2glb, adom-chip-laser.+set -e+git clone https://gitlab.com/kicad/libraries/kicad-footprint-generator.git kfg && cd kfg && git checkout 6ef686944ab44b3d3d75965a66730ac65d057e63+git apply ../kicad-generator-ds13560.patch      # UFQFPN-32 entry set to ST DS13560 Rev 6 Table 83 values+PYTHONPATH=src:. python3 src/generators/generate.py -g package/no_lead -p UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm -m ../gen+cd ..+# header: author/description rewritten to Adom (geometry bytes untouched), saved as stm32g0b1kbu6.step+adom-chip-laser etch stm32g0b1kbu6.step STM32G0B1KBU6 stm32g0b1kbu6-etched.step+for f in stm32g0b1kbu6 stm32g0b1kbu6-etched; do+  step2glb convert $f.step -o $f.raw.glb+  python3 glbmat.py $f.raw.glb $f.glb "0.019,0.018,0.018=0.0,0.55,Adom.Body (epoxy)" "0.645,0.638,0.572=1.0,0.35,Adom.Leads (matte tin)" "0.435,0.398,0.316=0.0,0.6,Adom.Pin1Mark"+done
provenance/tools/glbmat.pyadded+55
@@ -0,0 +1,55 @@+#!/usr/bin/env python3+"""Give a step2glb GLB physical materials (step2glb writes base colours only, so glTF's defaults, metallic 1 and+roughness 1, render every part as rough metal). Adapted from adom/stm32g431cbt6 provenance/tools/kicad-generator/+materials.py, keyed by base colour instead of node name because KiCad-generator STEPs are one fused solid.++usage: glbmat.py in.glb out.glb RULE [RULE ...]+  RULE = "r,g,b=metallic,roughness,Name"  (r,g,b = the GLB's linear baseColorFactor, matched within 0.02)+  The Adom.LaserEtch node's material always becomes metallic 0, roughness 0.7 (colour kept).+Geometry, node transforms, quantization and colours are untouched; materials that match no rule are reported."""+import sys+from pygltflib import GLTF2, PbrMetallicRoughness++def main(src, out, rules):+    R = []+    for r in rules:+        col, spec = r.split('=')+        m, ro, name = spec.split(',', 2)+        R.append(([float(v) for v in col.split(',')], float(m), float(ro), name))+    g = GLTF2().load(src)+    gen = g.asset.generator+    etch = set()+    for n in g.nodes:+        if n.mesh is not None and (n.name or '').startswith('Adom.LaserEtch'):+            etch |= {p.material for p in g.meshes[n.mesh].primitives}+    unmatched = []+    for i, m in enumerate(g.materials):+        pbr = m.pbrMetallicRoughness or PbrMetallicRoughness()+        c = list(pbr.baseColorFactor or [1, 1, 1, 1])+        if i in etch:+            pbr.metallicFactor, pbr.roughnessFactor = 0.0, 0.7; m.name = 'Adom.LaserEtch'+        else:+            hit = next((x for x in R if all(abs(a - b) <= 0.02 for a, b in zip(x[0], c[:3]))), None)+            if hit is None:+                unmatched.append((m.name, [round(v, 3) for v in c])); continue+            pbr.metallicFactor, pbr.roughnessFactor, m.name = hit[1], hit[2], hit[3]+        m.pbrMetallicRoughness = pbr+    g.asset.generator = gen  # keep the glTF-Transform stamp; the material pass is recorded in extras+    ex = g.asset.extras if isinstance(g.asset.extras, dict) else {}+    ex['adomMaterials'] = 'PBR metallic/roughness set by base colour (Adom glbmat.py); geometry untouched'+    g.asset.extras = ex+    g.save(out)+    # pygltflib stamps its own generator on save: put the glTF-Transform stamp back in the JSON chunk+    import json, struct+    b = open(out, 'rb').read(); cl = struct.unpack('<I', b[12:16])[0]+    j = json.loads(b[20:20 + cl]); j['asset']['generator'] = gen+    js = json.dumps(j, separators=(',', ':')).encode(); js += b' ' * ((4 - len(js) % 4) % 4)+    rest = b[20 + cl:]+    body = struct.pack('<I', len(js)) + b'JSON' + js + rest+    open(out, 'wb').write(b[:8] + struct.pack('<I', 12 + len(body)) + body)+    print(f'OK {out}: ' + '; '.join(f'{m.name} m{m.pbrMetallicRoughness.metallicFactor} r{m.pbrMetallicRoughness.roughnessFactor}' for m in g.materials))+    if unmatched:+        sys.exit(f'ERROR: materials matched no rule: {unmatched}')++if __name__ == '__main__':+    main(sys.argv[1], sys.argv[2], sys.argv[3:])
provenance/tools/kicad-generator-ds13560.patchadded+42
@@ -0,0 +1,42 @@+diff --git a/data/package/no_lead/qfn-3x.yaml b/data/package/no_lead/qfn-3x.yaml+index 0ccba12..b88a28f 100644+--- a/data/package/no_lead/qfn-3x.yaml++++ b/data/package/no_lead/qfn-3x.yaml+@@ -781,27 +781,22 @@ QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm:+ + UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm:+ # this is a UQFN, similar to JEDEC MO-248, variation UHHD-1 (but custom Exposed Pad from ST)+-  size_source: 'https://www.st.com/resource/en/datasheet/stm32g071k8.pdf'++# Adom: values from ST DS13560 Rev 6 (STM32G0B1xB/xC/xE), Table 83 UFQFPN32 mechanical data, p.131++#   A 0.50/0.55/0.60 (modelled at the typical 0.55), A1 0.00-0.05 (modelled 0), b 0.18/0.25/0.30,++#   D = E = 5.00 BSC, D2 = E2 3.40/3.50/3.60, e 0.50, L 0.30-0.50 (no typical printed; modelled at 0.40)++  size_source: 'https://www.st.com/resource/en/datasheet/stm32g0b1kb.pdf'+   device_type: 'UFQFPN'+-  body_size_x:+-    minimum: 4.9+-    nominal: 5+-    maximum: 5.1+-  body_size_y:+-    minimum: 4.9+-    nominal: 5+-    maximum: 5.1+-  overall_height:+-    minimum: 0.5+-    nominal: 0.55+-    maximum: 0.6++  body_size_x: 5.0++  body_size_y: 5.0++  body_pcb_gap: 0.0++  overall_height: 0.55+   num_pins_x: 8+   num_pins_y: 8+   pitch: 0.50+   lead_width:+     minimum: 0.18+-    nominal: 0.23+-    maximum: 0.28++    nominal: 0.25++    maximum: 0.30+   lead_len:+     minimum: 0.3+     nominal: 0.4
provenance/tools/ortho.pyadded+39
@@ -0,0 +1,39 @@+#!/usr/bin/env python3+"""ortho.py <step> <view> <px_per_mm> <out.png>  : orthographic hidden-line view of a STEP at an exact scale.+view: top (looking down -Z, +X right, +Y up) | bottom (looking up +Z, mirrored: +X left... drawn as seen from below,+      +X right, -Y up i.e. flipped about X) | front (looking +Y from -Y: +X right, +Z up) | back | left | right.+Writes out.png and out.json {px_per_mm, origin_px: pixel of (0,0) in the view plane, extents}."""+import json, re, sys+import cadquery as cq, cairosvg+step, view, ppm, out = sys.argv[1], sys.argv[2], float(sys.argv[3]), sys.argv[4]+s = cq.importers.importStep(step)+shape = cq.Compound.makeCompound(s.vals())+# rotate the shape so that the requested view becomes a top view (camera on +Z looking down, +X right, +Y up)+R = {'top': [], 'bottom': [((1, 0, 0), 180)], 'front': [((1, 0, 0), -90)], 'back': [((1, 0, 0), -90), ((0, 0, 1), 180)],+     'right': [((1, 0, 0), -90), ((0, 0, 1), -90)], 'left': [((1, 0, 0), -90), ((0, 0, 1), 90)]}[view]+for ax, ang in R:+    shape = shape.rotate(cq.Vector(0, 0, 0), cq.Vector(*ax), ang)+bb = shape.BoundingBox()+pad = 2.0+W, H = int((bb.xlen + 2 * pad) * ppm), int((bb.ylen + 2 * pad) * ppm)+# draw edges of a top view ourselves (cadquery's SVG autoscale is not exact); hidden-line removal via OCP HLR+from OCP.HLRBRep import HLRBRep_Algo, HLRBRep_HLRToShape+from OCP.HLRAlgo import HLRAlgo_Projector+from OCP.gp import gp_Ax2, gp_Pnt, gp_Dir+algo = HLRBRep_Algo(); algo.Add(shape.wrapped)+algo.Projector(HLRAlgo_Projector(gp_Ax2(gp_Pnt(0, 0, 0), gp_Dir(0, 0, 1), gp_Dir(1, 0, 0))))+algo.Update(); algo.Hide()+hl = HLRBRep_HLRToShape(algo)+paths = []+for comp in (hl.VCompound(), hl.OutLineVCompound(), hl.Rg1LineVCompound(), hl.RgNLineVCompound()):+    if comp is None or comp.IsNull(): continue+    for e in cq.Shape.cast(comp).Edges():+        pts = [e.positionAt(t / 40) for t in range(41)]+        d = 'M ' + ' L '.join(f'{(p.x - bb.xmin + pad) * ppm:.2f},{(bb.ymax + pad - p.y) * ppm:.2f}' for p in pts)+        paths.append(f'<path d="{d}" fill="none" stroke="#d00000" stroke-width="1.5"/>')+svg = f'<svg xmlns="http://www.w3.org/2000/svg" width="{W}" height="{H}">' + ''.join(paths) + '</svg>'+cairosvg.svg2png(bytestring=svg.encode(), write_to=out)+json.dump({'view': view, 'px_per_mm': ppm, 'origin_px': [(-bb.xmin + pad) * ppm, (bb.ymax + pad) * ppm],+           'extents_mm': [round(bb.xlen, 3), round(bb.ylen, 3)], 'x_mm': [bb.xmin, bb.xmax], 'y_mm': [bb.ymin, bb.ymax]},+          open(out.rsplit('.', 1)[0] + '.json', 'w'), indent=1)+print(out, W, H)
stm32g0b1kbu6-etched.glb
⋯ 1 unchanged line ⋯
stm32g0b1kbu6-etched.step+10181−12291
@@ -1,8 +1,8 @@ ISO-10303-21; HEADER; FILE_DESCRIPTION(('Open CASCADE Model'),'2;1');-FILE_NAME('Open CASCADE Shape Model','2026-10-16T23:26:31',('Author'),(-    'Open CASCADE'),'Open CASCADE STEP processor 7.9','Open CASCADE 7.9'+FILE_NAME('Open CASCADE Shape Model','2026-10-27T22:18:27',('Author'),(+    'Open CASCADE'),'Open CASCADE STEP processor 7.8','Open CASCADE 7.8'   ,'Unknown'); FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }')); ENDSEC;@@ -15,339 +15,321 @@ DATA; #4 = PRODUCT_DEFINITION_SHAPE('','',#5); #5 = PRODUCT_DEFINITION('design','',#6,#9); #6 = PRODUCT_DEFINITION_FORMATION('','',#7);-#7 = PRODUCT('STM32G0B1KBU6','STM32G0B1KBU6','',(#8));+#7 = PRODUCT('Adom.Chip','Adom.Chip','',(#8)); #8 = PRODUCT_CONTEXT('',#2,'mechanical'); #9 = PRODUCT_DEFINITION_CONTEXT('part definition',#2,'design');-#10 = SHAPE_REPRESENTATION('',(#11,#15,#19),#23);+#10 = ADVANCED_BREP_SHAPE_REPRESENTATION('',(#11,#15),#7046); #11 = AXIS2_PLACEMENT_3D('',#12,#13,#14); #12 = CARTESIAN_POINT('',(0.,0.,0.)); #13 = DIRECTION('',(0.,0.,1.)); #14 = DIRECTION('',(1.,0.,-0.));-#15 = AXIS2_PLACEMENT_3D('',#16,#17,#18);-#16 = CARTESIAN_POINT('',(0.,0.,0.));-#17 = DIRECTION('',(0.,0.,1.));-#18 = DIRECTION('',(1.,0.,-0.));-#19 = AXIS2_PLACEMENT_3D('',#20,#21,#22);-#20 = CARTESIAN_POINT('',(0.,0.,-3.E-03));-#21 = DIRECTION('',(0.,0.,1.));-#22 = DIRECTION('',(1.,0.,-0.));-#23 = ( GEOMETRIC_REPRESENTATION_CONTEXT(3) -GLOBAL_UNCERTAINTY_ASSIGNED_CONTEXT((#27)) GLOBAL_UNIT_ASSIGNED_CONTEXT(-(#24,#25,#26)) REPRESENTATION_CONTEXT('Context #1',-  '3D Context with UNIT and UNCERTAINTY') );-#24 = ( LENGTH_UNIT() NAMED_UNIT(*) SI_UNIT(.MILLI.,.METRE.) );-#25 = ( NAMED_UNIT(*) PLANE_ANGLE_UNIT() SI_UNIT($,.RADIAN.) );-#26 = ( NAMED_UNIT(*) SI_UNIT($,.STERADIAN.) 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