component

STM32G0B1KBU6

Public Made by Adom

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STMicroelectronics Microcontrollers, UFQFPN-32(5x5). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.

componentembedded processors & controllersstm32g0b1kbu6board-derived

Verified STM32G0B1KBU6

by Claude, at Caleb Taylor's request · last 28 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 6 records

28 Oct 2026Claude, at Caleb Taylor's requestValidated against ST's STM32G0B1xB/xC/xE datasheet DS13560 Rev 6 (February 2026)files match
SymbolFootprint3D modelPinsfor all variants
  • ✓Datasheet: replaced the LCSC copy (DS13560 Rev 3, January 2022) with ST's current DS13560 Rev 6, February 2026, from st.com
  • ✓Variant: STM32G0B1KBU6 = K 32 pins, B 128 KB, U UFQFPN, 6 = -40 to 85 C, no N option, so the GP pinout applies (ordering information p.161; N-suffix devices are the alternative pinout, p.11)
  • ✓All 33 pins match Figure 4 'STM32G0B1KxU UFQFPN32 pinout', GP version (p.37) and the LQFP32/UFQFPN32-GP column of Table 12 (p.47-55) by number and name, including PC14-OSC32_IN, PC15-OSC32_OUT, VDD/VDDA, VSS/VSSA, PF2-NRST, PA11 [PA9], PA12 [PA10], PA14-BOOT0; pin 33 is the exposed pad, labelled VSS in Figure 4. No renames needed
  • ✓Pin types agree with Table 12: the 30 port pins are I/O (bidirectional; PF2-NRST is RST/FT), VDD/VDDA and VSS/VSSA are supply (power_in); exposed pad 33 changed passive -> power_in (VSS ground)
  • ✓All 33 descriptions rewritten from Table 12 rows (I/O structure decoded with Table 11 p.46, alternate and additional functions, notes 1-6 on p.55), the power supply scheme (p.17) and Figure 4; citations re-pointed from Rev 3 to Rev 6 pages
  • •Footprint (designer custom STM_CDT UFQFPN-32-1EP 5x5) vs Figure 41/Table 83 (p.130-131) and Figure 42 footprint example (p.133): 32 pads 0.25 mm wide on e = 0.50 mm, as Figure 42; pads 0.875 mm long with centres at +/-2.4375 mm (span 2.00 to 2.875 mm from centre) vs Figure 42's 0.65 mm pads in a 5.50 mm outline (2.10 to 2.75 mm): longer by 0.10 mm inward and 0.125 mm outward, still covering the terminals (D/2 = 2.50, L 0.30-0.50, b 0.18-0.30) with 0.25 mm clearance to the exposed pad; exposed pad 3.50 x 3.50 mm = Figure 42 and D2/E2 typ (3.40-3.60), with four 1.41 mm paste windows; pin 1 at the top of the left column, numbering counter-clockwise as Figure 42
  • ✓3D model rebuilt (tier 3): the previous model was extracted from a board STEP with no licence. Tier 1 unusable (ST's CAD sits behind a my.st.com login/e-mail validation via SamacSys/Ultra Librarian, whose terms forbid library redistribution); tier 2 unusable (KiCad has no UFQFPN-32 EP3.5 model; QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm is 0.77 mm tall vs A 0.50-0.60). Generated with kicad-footprint-generator @ 6ef68694 package/no_lead at DS13560 Table 83 values (patch in provenance/tools), CC-BY-SA-4.0
  • ✓3D body vs Figure 41/Table 83 (p.130-131): 5.00 x 5.00 x 0.55 mm (D = E 5.00 BSC, A 0.50-0.60); 32 terminals 0.40 x 0.25 mm at the edge on e = 0.50 (L 0.30-0.50, b 0.18-0.30), centres on the footprint pad centres; exposed pad 3.50 x 3.50 mm (D2/E2 3.40-3.60); pin-1 dimple top-left over pad 1 and bottom view pin 1 lower left as Figure 41 (docs/proof/stm32g0b1kbu6-3d-model.png)
  • ✓Pose: stm32g0b1kbu6.step and -etched.step Z-up, seated on z = 0, centred on the pad pattern (offset 0), footprint model binding identity (step_pose.py PASS); MPN etched on the top face with adom-chip-laser 0.2.0; GLBs from step2glb 0.13.2 (glTF-Transform, KHR_mesh_quantization) with PBR materials set by colour
  • •Not modelled: Figure 41's exposed-pad terminal-1 chamfer and corner radii (undimensioned, figure not to scale); terminal thickness A3 (not printed) left at the generator's 0.11 mm
  • ✓DigiKey 497-STM32G0B1KBU6-ND and Mouser 511-STM32G0B1KBU6 confirmed as STM32G0B1KBU6 by STMicroelectronics (2026-10-27)
  • ✓Symbol Datasheet / MPN / Manufacturer / DigiKey / Mouser / LCSC properties agree with page.json; footprint Datasheet property points at the manufacturer datasheet URL
  • ✓component-page-verify: all checks pass; adom-lbr validate OK
Evidencedatasheet (STMicroelectronics, DS13560 Rev 6)3D model views vs Figure 413D model provenance
Verified files✓ stm32g0b1kbu6.kicad_sym✓ stm32g0b1kbu6.kicad_mod✓ stm32g0b1kbu6.step
16 Oct 2026Claude (AI build)Datasheet pins not matched to a symbol pin: EPsuperseded
reviewfor all variants
  • •Datasheet pins not matched to a symbol pin: EP
16 Oct 2026Claude (AI build)3D model provenance: extracted from the source board STEP export (designer custom library ...superseded
reviewfor all variants
  • •3D model provenance: extracted from the source board STEP export (designer custom library STM_CDT); the upstream model licence is not stated, so the page licence is NOASSERTION.
16 Oct 2026Claude (AI build)Footprint is the designer custom STM_CDT:STM32G0B1_UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm;...superseded
reviewfor all variants
  • •Footprint is the designer custom STM_CDT:STM32G0B1_UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm; check it against the UFQFPN32 package drawing.
16 Oct 2026Claude (AI build)Symbol pin names changed to the datasheet spelling (Figure 12, GP version): PC14-OSC32_IN,...superseded
reviewfor all variants
  • •Symbol pin names changed to the datasheet spelling (Figure 12, GP version): PC14-OSC32_IN, PC15-OSC32_OUT, VDD/VDDA, VSS/VSSA, PF2-NRST, PA9, PA10, PA11 [PA9], PA12 [PA10], PA14-BOOT0.
16 Oct 2026Claude (AI build)Automated build checks (awaiting human validation)superseded
SymbolFootprint3D modelPinsfor all variants
  • ✓Footprint extracted pad-for-pad from the source board and normalized to the footprint frame (back-side parts un-mirrored)
  • ✓3D model seated z=0 at footprint origin (placement inverse; method centroid-matched to KiCad library models on 59 cases)
  • ✓adom-lbr generate + lint passed
  • ✓33 of 33 pins described from the datasheet (adom-ds2sf, page-cited)
  • •Not yet checked by a person: land pattern vs datasheet, pin-1/orientation, 3D body vs drawing
Evidencedatasheet
Verified files! stm32g0b1kbu6.kicad_sym✓ stm32g0b1kbu6.kicad_mod! stm32g0b1kbu6.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
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← Commit history

Add component metadata and pin table

Caleb ·5c4f82551f ·12d ago ·parent e76661e
1 file changed +323−30
page.json+323−30
page.json+323−30
@@ -1,28 +1,35 @@ {   "schema_version": 1,-  "slug": "stm32g0b1kbu6",   "type": "component",-  "kind": "component",+  "slug": "stm32g0b1kbu6",   "title": "STM32G0B1KBU6",   "brief": "STMicroelectronics Microcontrollers, UFQFPN-32(5x5). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.",   "version": "0.1.0",-  "because": "No wiki page exists for this MPN: searched the wiki registry by MPN, slug and LCSC number on 2026-10-16 under every owner; no match.",-  "hero": {-    "type": "billboard",-    "headline": "STM32G0B1KBU6",-    "subhead": "STMicroelectronics Microcontrollers",-    "screenshot": "docs/hero.png",-    "chrome": false-  },+  "license": "NOASSERTION",+  "tags": [+    "component",+    "embedded processors & controllers",+    "stm32g0b1kbu6",+    "board-derived",+    "staged-for-validation"+  ],   "component": {     "mpn": "STM32G0B1KBU6",     "manufacturer": "STMicroelectronics",     "package": "UFQFPN-32(5x5)",-    "pin_count": null,+    "pin_count": 33,     "category": "Embedded Processors & Controllers",     "subcategory": "Microcontrollers",-    "body_size": null,-    "parts": {},+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834535048413184",+    "parts": {+      "symbol": "stm32g0b1kbu6.kicad_sym",+      "footprint": "stm32g0b1kbu6.kicad_mod",+      "model_3d": "stm32g0b1kbu6-etched.glb",+      "model_3d_plain": "stm32g0b1kbu6.glb",+      "model_3d_step": "stm32g0b1kbu6-etched.step",+      "model_3d_step_plain": "stm32g0b1kbu6.step",+      "lbr": "stm32g0b1kbu6.lbr"+    },     "distributor_links": {       "digikey": {         "part": "497-STM32G0B1KBU6-ND",@@ -37,31 +44,317 @@         "url": "https://www.lcsc.com/product-detail/C5159549.html"       }     },-    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834535048413184"+    "pins": [+      {+        "number": "1",+        "name": "PB9",+        "type": "bidirectional",+        "description": "General-purpose I/O PB9. 5 V-tolerant, Fm+ I2C capable. Alt-functions: IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. [datasheet p.47]"+      },+      {+        "number": "2",+        "name": "PC14-OSC32_IN",+        "type": "bidirectional",+        "description": "GPIO PC14 or 32 kHz LSE crystal input (OSC32_IN). 5 V-tolerant; supplied through RTC-domain power switch (limited to ~3 mA when used as GPIO). Alt-function: TIM1_BKIN2. Additional: OSC32_IN, OSC_IN. [datasheet p.47]"+      },+      {+        "number": "3",+        "name": "PC15-OSC32_OUT",+        "type": "bidirectional",+        "description": "GPIO PC15 or 32 kHz LSE crystal output (OSC32_OUT). 5 V-tolerant; supplied through RTC-domain power switch (limited to ~3 mA). Alt-functions: OSC32_EN, OSC_EN, TIM15_BKIN. Additional: OSC32_OUT. [datasheet p.47]"+      },+      {+        "number": "4",+        "name": "VDD/VDDA",+        "type": "power_in",+        "description": "Combined digital core/digital I/O supply (VDD) and analog supply (VDDA). Operating range 1.7 V to 3.6 V. Decouple with 100 nF ceramic + bulk capacitor to VSS/VSSA. [datasheet p.47]"+      },+      {+        "number": "5",+        "name": "VSS/VSSA",+        "type": "power_in",+        "description": "Combined digital and analog ground reference (VSS and VSSA tied together). [datasheet p.47]"+      },+      {+        "number": "6",+        "name": "PF2-NRST",+        "type": "bidirectional",+        "description": "Bidirectional NRST reset pin with embedded weak pull-up (RST), active low. Can be reconfigured as GPIO PF2. Alt-functions when GPIO: MCO, LPUART2_TX, LPUART2_RTS_DE. Additional: NRST. [datasheet p.47]"+      },+      {+        "number": "7",+        "name": "PA0",+        "type": "bidirectional",+        "description": "GPIO PA0 with analog-switch feature (FT_a). ADC_IN0, COMP1_INM8. Alt-functions: SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT. Additional: TAMP_IN2, WKUP1. [datasheet p.48]"+      },+      {+        "number": "8",+        "name": "PA1",+        "type": "bidirectional",+        "description": "GPIO PA1 with analog-switch + switchable diode (FT_ea). ADC_IN1, COMP1_INP2. Alt-functions: SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT. [datasheet p.48]"+      },+      {+        "number": "9",+        "name": "PA2",+        "type": "bidirectional",+        "description": "GPIO PA2 (FT_a). ADC_IN2, COMP2_INM8, WKUP4, LSCO. Alt-functions: SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT. [datasheet p.48]"+      },+      {+        "number": "10",+        "name": "PA3",+        "type": "bidirectional",+        "description": "GPIO PA3 (FT_ea). ADC_IN3, COMP2_INP2. Alt-functions: SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT. [datasheet p.48]"+      },+      {+        "number": "11",+        "name": "PA4",+        "type": "bidirectional",+        "description": "GPIO PA4 (TT_a — 3.6 V tolerant, analog-switch). ADC_IN4, DAC1_OUT1. Alt-functions: SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS. Additional (32-pin only): TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. [datasheet p.48]"+      },+      {+        "number": "12",+        "name": "PA5",+        "type": "bidirectional",+        "description": "GPIO PA5 (TT_ea — 3.6 V tolerant). ADC_IN5, DAC1_OUT2. Alt-functions: SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT. [datasheet p.48]"+      },+      {+        "number": "13",+        "name": "PA6",+        "type": "bidirectional",+        "description": "GPIO PA6 (FT_ea). ADC_IN6. Alt-functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA. [datasheet p.48]"+      },+      {+        "number": "14",+        "name": "PA7",+        "type": "bidirectional",+        "description": "GPIO PA7 (FT_a). ADC_IN7. Alt-functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL. [datasheet p.48]"+      },+      {+        "number": "15",+        "name": "PB0",+        "type": "bidirectional",+        "description": "GPIO PB0 (FT_ea). ADC_IN8, COMP3_INP0. Alt-functions: SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS. [datasheet p.49]"+      },+      {+        "number": "16",+        "name": "PB1",+        "type": "bidirectional",+        "description": "GPIO PB1 (FT_ea). ADC_IN9, COMP1_INM6. Alt-functions: TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE. [datasheet p.49]"+      },+      {+        "number": "17",+        "name": "PB2",+        "type": "bidirectional",+        "description": "GPIO PB2 (FT_ea). ADC_IN10, COMP1_INP1, COMP3_INM6. Alt-functions: SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT. [datasheet p.49]"+      },+      {+        "number": "18",+        "name": "PA8",+        "type": "bidirectional",+        "description": "GPIO PA8 (FT_fcs — 5 V, Fm+, USB-C PD capable, VDDIO2-selectable). Additional UCPD1_CC1. Alt-functions: MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA. [datasheet p.51]"+      },+      {+        "number": "19",+        "name": "PA9",+        "type": "bidirectional",+        "description": "GPIO PA9 (FT_fds — 5 V, Fm+, USB-C Dead-Battery capable). Additional UCPD1_DBCC1. Alt-functions: MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL. [datasheet p.51]"+      },+      {+        "number": "20",+        "name": "PC6",+        "type": "bidirectional",+        "description": "GPIO PC6 (FT_s — 5 V, VDDIO2-only supplied). Alt-functions: UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. [datasheet p.51]"+      },+      {+        "number": "21",+        "name": "PA10",+        "type": "bidirectional",+        "description": "GPIO PA10 (FT_fds). Additional UCPD1_DBCC2. Alt-functions: SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA. [datasheet p.51]"+      },+      {+        "number": "22",+        "name": "PA11 [PA9]",+        "type": "bidirectional",+        "description": "GPIO PA11 (FT_fs) by default; remappable to PA9 via SYSCFG_CFGR1. Carries USB_DM (D-) when USB is enabled. Alt-functions: SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT. [datasheet p.51]"+      },+      {+        "number": "23",+        "name": "PA12 [PA10]",+        "type": "bidirectional",+        "description": "GPIO PA12 (FT_fs) by default; remappable to PA10. Carries USB_DP (D+) when USB is enabled. Alt-functions: SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT. [datasheet p.51]"+      },+      {+        "number": "24",+        "name": "PA13",+        "type": "bidirectional",+        "description": "GPIO PA13 (FT_es). SWDIO after reset with internal pull-up active. Alt-functions: SWDIO, IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. [datasheet p.52]"+      },+      {+        "number": "25",+        "name": "PA14-BOOT0",+        "type": "bidirectional",+        "description": "GPIO PA14 (FT_s) with BOOT0 additional function sampled at reset through internal pull-down. SWCLK after reset. Alt-functions: SWCLK, USART2_TX, EVENTOUT, LPUART2_TX. Additional: BOOT0. [datasheet p.52]"+      },+      {+        "number": "26",+        "name": "PA15",+        "type": "bidirectional",+        "description": "GPIO PA15 (FT_s). Alt-functions: SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. [datasheet p.52]"+      },+      {+        "number": "27",+        "name": "PB3",+        "type": "bidirectional",+        "description": "GPIO PB3 (FT_a). COMP2_INM6. Alt-functions: SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK. [datasheet p.54]"+      },+      {+        "number": "28",+        "name": "PB4",+        "type": "bidirectional",+        "description": "GPIO PB4 (FT_a). COMP2_INP0. Alt-functions: SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO. [datasheet p.54]"+      },+      {+        "number": "29",+        "name": "PB5",+        "type": "bidirectional",+        "description": "GPIO PB5 (FT). Additional WKUP6. Alt-functions: SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI. [datasheet p.54]"+      },+      {+        "number": "30",+        "name": "PB6",+        "type": "bidirectional",+        "description": "GPIO PB6 (FT_fa — 5 V, Fm+, analog-switch). COMP2_INP1. Alt-functions: USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX. [datasheet p.55]"+      },+      {+        "number": "31",+        "name": "PB7",+        "type": "bidirectional",+        "description": "GPIO PB7 (FT_fa). COMP2_INM7, PVD_IN. Alt-functions: USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX. [datasheet p.55]"+      },+      {+        "number": "32",+        "name": "PB8",+        "type": "bidirectional",+        "description": "GPIO PB8 (FT_f — 5 V, Fm+ capable). Alt-functions: CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. [datasheet p.55]"+      },+      {+        "number": "33",+        "name": "VSS",+        "type": "passive",+        "description": "Exposed pad; labelled VSS in the UFQFPN32 GP-version pinout (Figure 12). [datasheet p.45]"+      }+    ],+    "provenance": {+      "factory_chain": {+        "pipeline": "adom-parts (board-derived) 0.1",+        "pins": "KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7)",+        "at": "2026-10-16"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834535048413184",+        "pages": 159,+        "sha256": "19ad77934ee0849dbf613999149675086b13912adbafca09b8c37b8bfa76b053",+        "source_tier": "lcsc"+      },+      "cad": "Footprint, symbol and 3D model as used on Adom board designs; the 3D model was extracted from the board STEP export",+      "pins": {+        "total": 33,+        "described": 33,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "stm32g0b1kbu6.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin",+        "seat": "z = 0 (PCB top surface)",+        "extents_mm": [+          5.0,+          5.0,+          0.55+        ],+        "zmin_mm": -0.0,+        "footprint_binding": "identity",+        "sha256": "d78e7cbde5c638c998f2a03f4a479341b393764138cdd65a74485c919619a77d",+        "checked": "2026-10-16",+        "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+      },+      {+        "file": "stm32g0b1kbu6-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin",+        "seat": "z = 0 (PCB top surface)",+        "extents_mm": [+          5.0,+          5.0,+          0.552+        ],+        "zmin_mm": -0.0,+        "footprint_binding": "identity",+        "sha256": "a81d15c854269feed566681fcca9c14d064d445d8b32ba2a9f15aa1a746881fe",+        "checked": "2026-10-16",+        "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+      }+    ]   },-  "tags": [-    "component",-    "embedded processors & controllers",-    "stm32g0b1kbu6",-    "board-derived",-    "staged-for-validation"+  "metadata": {+    "specs": {+      "Manufacturer": "STMicroelectronics",+      "Package": "UFQFPN-32(5x5)",+      "Category": "Embedded Processors & Controllers",+      "Pins": "33",+      "LCSC": "C5159549"+    }+  },+  "variants": [],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"   ],   "discovery_triggers": [     "stm32g0b1kbu6",     "stm32g0b1kbu6"   ],-  "license": "NOASSERTION",-  "visibility": {-    "public": false-  },+  "discovery_pitch": "STM32G0B1KBU6 (STMicroelectronics) component page: pinout, KiCad symbol, footprint and 3D.",   "author": {     "name": "Caleb",     "email": "[email protected]"   },-  "sample_prompts": [],-  "discovery_pitch": null,-  "metadata": {},-  "created_at": "2026-10-16T23:36:47.321Z",-  "updated_at": "2026-10-16T23:36:47.321Z",-  "org": "adom"+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "verification.json",+    "stm32g0b1kbu6.kicad_sym",+    "stm32g0b1kbu6.kicad_mod",+    "stm32g0b1kbu6-etched.glb",+    "stm32g0b1kbu6-etched.step",+    "stm32g0b1kbu6.glb",+    "stm32g0b1kbu6.step",+    "stm32g0b1kbu6.lbr",+    "docs/hero.png",+    "docs/stm32g0b1kbu6-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": {+    "public": false+  } }\ No newline at end of file