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STM32G071KBT3

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32g071kbt3factory-2.0.0extractor-text
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STM32G071KBT3

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM32G071KBT3 from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB9 bidirectional 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions including I2C1_SDA, USART3_RX, TIM17_CH1, SPI2_NSS and IR_OUT.
2 PC14-OSC32_IN bidirectional 5 V-tolerant GPIO supplied through the RTC-domain power switch, which sinks at most 3 mA, so output speed must not exceed 2 MHz at 30 pF and it must not be used as a current source; it is also the 32.768 kHz oscillator input OSC32_IN.
3 PC15-OSC32_OUT bidirectional 5 V-tolerant GPIO on the same RTC-domain power switch with the same 3 mA sink and 2 MHz / 30 pF output-speed limits as PC14; it is also the 32.768 kHz oscillator output OSC32_OUT.
4 VDD/VDDA power_in Main supply for the I/Os, internal regulator and analog blocks, specified from 1.7 V to 3.6 V for VDD, with VDDA from 1.62 V for ADC and COMP (1.8 V for DAC, 2.4 V for VREFBUF) up to 3.6 V.
5 VSS/VSSA power_in Ground reference for the digital and analog supplies; all voltages in the datasheet are referenced to VSS.
6 PF2-NRST bidirectional Bidirectional reset pin with an embedded weak pull-up resistor (NRST), also usable as a 5 V-tolerant GPIO (PF2) with MCO alternate function.
7 PA0 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing ADC_IN0, COMP1_INM and TAMP_IN2/WKUP1 analog or wakeup functions alongside SPI2_SCK, USART2_CTS and TIM2_CH1_ETR.
8 PA1 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing ADC_IN1 and COMP1_INP alongside SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK and TIM2_CH2.
9 PA2 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing ADC_IN2, COMP2_INM and WKUP4 alongside SPI1_MOSI/I2S1_SD, USART2_TX and LPUART1_TX.
10 PA3 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing ADC_IN3 and COMP2_INP alongside SPI2_MISO, USART2_RX and LPUART1_RX.
11 PA4 bidirectional 3.6 V-tolerant I/O (TT_a, input may go up to VDD+0.3 V), providing ADC_IN4, DAC_OUT1 and RTC_OUT2 alongside SPI1_NSS/I2S1_WS, SPI2_MOSI and TIM14_CH1.
12 PA5 bidirectional 3.6 V-tolerant I/O (TT_a, input may go up to VDD+0.3 V), providing ADC_IN5 and DAC_OUT2 alongside SPI1_SCK/I2S1_CK, CEC and USART3_TX.
13 PA6 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing ADC_IN6 alongside SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN and LPUART1_CTS.
14 PA7 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing ADC_IN7 alongside SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N and COMP2_OUT.
15 PB0 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing ADC_IN8 alongside SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, USART3_RX and UCPD1_FRSTX.
16 PB1 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing COMP1_INM and ADC_IN9 alongside TIM14_CH1, TIM3_CH4, TIM1_CH3N and LPUART1_RTS_DE.
17 PB2 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing COMP1_INP and ADC_IN10 alongside SPI2_MISO, USART3_TX and LPTIM1_OUT; this pin exists only in the GP version.
18 PA8 bidirectional 5 V-tolerant I/O (FT_c, VIN up to 5.0 V) with alternate functions MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT and UCPD1_CC1; a pull-down may be present at reset and can be disabled by strobing UCPDx_STROBE in SYSCFG_CFGR1 during start-up.
19 PA9 bidirectional 5 V-tolerant Fm+-capable I/O with USB Type-C dead-battery function (FT_fd); alternate functions include MCO, USART1_TX, TIM1_CH2 and I2C1_SCL, and a pull-down may be present at reset that can be disabled through SYSCFG_CFGR1 UCPDx_STROBE.
20 PC6 bidirectional 5 V-tolerant I/O (FT) with alternate functions UCPD1_FRSTX, TIM3_CH1 and TIM2_CH3.
21 PA10 bidirectional 5 V-tolerant Fm+-capable I/O with USB Type-C dead-battery function (FT_fd); alternate functions include SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN and I2C1_SDA, and a pull-down may be present at reset that can be disabled through SYSCFG_CFGR1 UCPDx_STROBE.
22 PA11 [PA9] bidirectional 5 V-tolerant Fm+-capable I/O (FT_f) whose default mapping is PA11, with alternate functions SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL and COMP1_OUT; PA9 can be remapped to this pin via SYSCFG_CFGR1.
23 PA12 [PA10] bidirectional 5 V-tolerant Fm+-capable I/O (FT_f) whose default mapping is PA12, with alternate functions SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA and COMP2_OUT; PA10 can be remapped to this pin via SYSCFG_CFGR1.
24 PA13 bidirectional 5 V-tolerant I/O (FT) that after reset is the SWDIO debug function with internal pull-up activated, also providing IR_OUT and EVENTOUT.
25 PA14-BOOT0 bidirectional 5 V-tolerant I/O (FT) that after reset is the SWCLK debug function with internal pull-down activated, and serves as the BOOT0 boot-mode pin when the boot selector option bit enables it.
26 PA15 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, USART4_RTS_DE_CK and USART3_RTS_DE_CK; this pin is present only in the GP version.
27 PB3 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing COMP2_INM alongside SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2 and USART1_RTS_DE_CK.
28 PB4 bidirectional 5 V-tolerant I/O with analog switch function (FT_a), providing COMP2_INP alongside SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS and TIM17_BKIN.
29 PB5 bidirectional 5 V-tolerant I/O (FT) with wakeup function WKUP6, alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1, I2C1_SMBA and COMP2_OUT.
30 PB6 bidirectional 5 V-tolerant Fm+-capable I/O with analog switch function (FT_fa), providing COMP2_INP alongside USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR and I2C1_SCL.
31 PB7 bidirectional 5 V-tolerant Fm+-capable I/O with analog switch function (FT_fa), providing COMP2_INM and PVD_IN alongside USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2 and I2C1_SDA.
32 PB8 bidirectional 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions CEC, SPI2_SCK, TIM16_CH1, USART3_TX, TIM15_BKIN and I2C1_SCL.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

CAD (KiCad official)

  • Symbol: STM32G071KBT3
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32g071kbt3-etched.step / stm32g071kbt3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g071kbt3.step / stm32g071kbt3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (133 pp, sha256 96d7e9ca1500e794, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF