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STM32G071K8U6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-32(5x5). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32G071K8U6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-32(5x5)

STM32G071K8U6 from STMicroelectronics, in a UFQFPN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB9 bidirectional 5 V-tolerant FT_f I/O with Fm+ capability, with alternate functions including IR_OUT, UCPD2_FRSTX, TIM17_CH1, USART3_RX, SPI2_NSS, I2C1_SDA and EVENTOUT.
2 PC14-OSC32_IN bidirectional FT I/O supplied through the power switch, sinking only a limited current (3 mA), so output speed must not exceed 2 MHz at 30 pF and it must not source current such as driving an LED; it also serves as the OSC32_IN oscillator input.
3 PC15-OSC32_OUT bidirectional FT I/O supplied through the power switch, sinking only a limited current (3 mA), so output speed must not exceed 2 MHz at 30 pF and it must not source current such as driving an LED; it also serves as the OSC32_OUT oscillator output.
4 VDD/VDDA power_in Main supply pin for the device and the analog supplies, operating from 1.7 V to 3.6 V.
5 VSS/VSSA power_in Ground pin for the digital and analog supply domains.
6 PF2-NRST bidirectional Active-low reset pin with an embedded weak pull-up resistor, operating as an FT I/O when configured as GPIO.
7 PA0 bidirectional FT_a I/O that also provides ADC input channel 0, COMP1 inverting input, and WKUP1 wakeup function.
8 PA1 bidirectional FT_a I/O that also provides ADC input channel 1 and COMP1 non-inverting input.
9 PA2 bidirectional FT_a I/O that also provides ADC input channel 2, COMP2 inverting input, WKUP4 and LSCO.
10 PA3 bidirectional FT_a I/O that also provides ADC input channel 3 and COMP2 non-inverting input.
11 PA4 bidirectional TT_a I/O (3.6 V tolerant) that also provides ADC input channel 4, DAC_OUT1 and RTC_OUT2.
12 PA5 bidirectional TT_a I/O (3.6 V tolerant) that also provides ADC input channel 5 and DAC_OUT2.
13 PA6 bidirectional FT_a I/O that also provides ADC input channel 6 and COMP1_OUT alternate function.
14 PA7 bidirectional FT_a I/O that also provides ADC input channel 7 and COMP2_OUT alternate function.
15 PB0 bidirectional FT_a I/O that also provides ADC input channel 8 and COMP1_OUT alternate function.
16 PB1 bidirectional FT_a I/O that also provides ADC input channel 9 and COMP1 inverting input.
17 PB2 bidirectional FT_a I/O that also provides ADC input channel 10 and COMP1 non-inverting input.
18 PA8 bidirectional FT_c I/O with USB Type-C PD capability, also providing MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT and UCPD1_CC1; a pull-down may be present at reset.
19 PA9 bidirectional FT_fd I/O with Fm+ capability and USB Type-C PD dead-battery function, also providing MCO, USART1_TX, TIM1_CH2, I2C1_SCL and UCPD1_DBCC1.
20 PC6 bidirectional FT I/O that also provides UCPD1_FRSTX, TIM3_CH1 and TIM2_CH3 alternate functions.
21 PA10 bidirectional FT_fd I/O with Fm+ capability and USB Type-C PD dead-battery function, also providing SPI2_MOSI, USART1_RX, TIM1_CH3, I2C1_SDA and UCPD1_DBCC2.
22 PA11 [PA9] bidirectional FT_f I/O with Fm+ capability that can be remapped in place of PA9 via SYSCFG_CFGR1, also providing USART1_CTS, TIM1_CH4, I2C2_SCL and COMP1_OUT.
23 PA12 [PA10] bidirectional FT_f I/O with Fm+ capability that can be remapped in place of PA10 via SYSCFG_CFGR1, also providing SPI1_MOSI, USART1_RTS_DE_CK, TIM1_ETR, I2C2_SDA and COMP2_OUT.
24 PA13 bidirectional FT I/O that is configured as the SWDIO debug function upon reset, with an internal pull-up enabled, and also provides IR_OUT and EVENTOUT.
25 PA14-BOOT0 bidirectional FT I/O that is configured as the SWCLK debug function upon reset with an internal pull-down enabled, and also serves as the BOOT0 boot pin.
26 PA15 bidirectional FT I/O that also provides SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, USART4_RTS_DE_CK, USART3_RTS_DE_CK and EVENTOUT.
27 PB3 bidirectional FT_a I/O that also provides SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK and EVENTOUT alternate functions, plus the COMP2 inverting input.
28 PB4 bidirectional FT_a I/O that also provides SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN and EVENTOUT alternate functions, plus the COMP2 non-inverting input.
29 PB5 bidirectional FT I/O that also provides SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1, I2C1_SMBA and COMP2_OUT alternate functions, plus the WKUP6 wakeup function.
30 PB6 bidirectional FT_fa I/O with Fm+ capability that also provides USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, EVENTOUT and the COMP2 non-inverting input.
31 PB7 bidirectional FT_fa I/O with Fm+ capability that also provides USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, the COMP2 inverting input and PVD_IN.
32 PB8 bidirectional FT_f I/O with Fm+ capability that also provides CEC, SPI2_SCK, TIM16_CH1, USART3_TX, TIM15_BKIN, I2C1_SCL and EVENTOUT.
33 EP passive Exposed pad (ST Figure 6 labels it Exposed pad); named EP as on the other STM32 UFQFPN32 pages.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD, absolute maximum VDD -0.3 4 V External supply voltage 55
Backup supply voltage on VBAT pin, absolute maximum VBAT -0.3 4 V External supply voltage on VBAT pin 55
Input voltage on FT_c pins, absolute maximum VIN -0.3 5.5 V Input voltage on FT_c pins 55
Input voltage on any other pin, absolute maximum VIN -0.3 4 V Input voltage on any other pin 55
Current into VDD/VDDA power pin (source) IVDD/VDDA 100 mA 55
Current out of VSS/VSSA ground pin (sink) IVSS/VSSA 100 mA 55
Output current sunk by any I/O and control pin IIO(PIN) 15 mA except FT_f pin 55
Output current sunk by any FT_f pin IIO(PIN) 20 mA FT_f pin 55
Output current sourced by any I/O and control pin IIO(PIN) 15 mA 55
Total output current sunk by sum of all I/Os and control pins ΣIIO(PIN) 80 mA 55
Total output current sourced by sum of all I/Os and control pins ΣIIO(PIN) 80 mA 56
Injected current on a FT_xx pin IINJ(PIN) -5 mA FT_xx pin; positive injection not possible (NA) 56
Injected current on a TT_a pin IINJ(PIN) -5 0 mA TT_a pin 56
Total injected current (sum of all I/Os and control pins) ΣIINJ(PIN) 25 mA absolute sum of negative injected currents 56
Storage temperature range TSTG -65 150 °C 56
Maximum junction temperature TJ 150 °C 56
Internal AHB clock frequency fHCLK 0 64 MHz 56
Internal APB clock frequency fPCLK 0 64 MHz 56
Standard operating voltage VDD 1.7 3.6 V 56
Analog supply voltage for ADC and COMP VDDA 1.62 3.6 V For ADC and COMP operation 56
Analog supply voltage for DAC VDDA 1.8 3.6 V For DAC operation 56
Backup operating voltage VBAT 1.55 3.6 V 56
I/O input voltage on FT_c pins VIN -0.3 5 V FT_c pins 56
Ambient temperature, suffix 6 TA -40 85 °C Suffix 6 (temperature range digit 6 in order code) 57
Junction temperature, suffix 6 TJ -40 105 °C Suffix 6 57
VDD slew rate, falling tVDD 10 µs/V VDD falling; ULPEN = 0 57
POR temporization when VDD crosses VPOR tRSTTEMPO 250 400 µs VDD rising 57
Power-on reset threshold VPOR 1.62 1.66 1.7 V 57
Power-down reset threshold VPDR 1.6 1.64 1.69 V 57
Brownout reset threshold 1, rising VBOR1 2.05 2.1 2.18 V VDD rising 57
Brownout reset threshold 1, falling VBOR1 1.95 2 2.08 V VDD falling 57
Brownout reset threshold 2, rising VBOR2 2.2 2.31 2.38 V VDD rising 57
Brownout reset threshold 2, falling VBOR2 2.1 2.21 2.28 V VDD falling 57
Brownout reset threshold 3, rising VBOR3 2.5 2.62 2.68 V VDD rising 57
Brownout reset threshold 3, falling VBOR3 2.4 2.52 2.58 V VDD falling 57
Hysteresis of VBORx and VPVDx Vhyst_BOR_PVD 100 mV 57
BOR and PVD consumption IDD(BOR_PVD) 1.1 1.6 µA Specified by design, not tested in production 57
Internal reference voltage VREFINT 1.182 1.212 1.232 V -40°C < TJ < 130°C 58
VREFINT buffer consumption from VDD when converted by ADC IDD(VREFINTBUF) 12.5 20 µA 58
Internal reference voltage spread over the temperature range ΔVREFINT 5 7.5 mV VDD = 3 V 58
Temperature coefficient TCoeff_vrefint 30 50 ppm/°C 58
Long term stability ACoeff 300 1000 ppm 1000 hours, T = 25 °C 58
Voltage coefficient VDDCoeff 250 1200 ppm/V 3.0 V < VDD < 3.6 V 58
1/4 reference voltage VREFINT_DIV1 24 25 26 % VREFINT 58
Supply current in Run mode IDD(Run) 6.3 7.7 mA Range 1; PLL enabled; fHCLK = 64 MHz; flash memory; typ at 25 °C, max at 130 °C 60
Supply current in Sleep mode IDD(Sleep) 1.8 2.9 mA Range 1; fHCLK = 64 MHz; flash memory enabled; all peripherals disabled; typ at 25 °C, max at 130 °C 63
Supply current in Stop 0 mode IDD(Stop 0) 285 1020 µA HSI kernel enabled; VDD = 3.6 V; typ at 25 °C, max at 130 °C 63
Supply current in Standby mode IDD(Standby) 0.34 55 µA RTC disabled; VDD = 3.6 V; typ at 25 °C, max at 130 °C 64
Supply current in Shutdown mode IDD(Shutdown) 53 43600 nA RTC disabled; VDD = 3.6 V; typ at 25 °C, max at 130 °C 65
User external clock source frequency fHSE_ext 8 48 MHz Voltage scaling Range 1 70
User external clock source frequency fHSE_ext 8 26 MHz Voltage scaling Range 2 70
OSC_IN high or low time tw(HSEH), tw(HSEL) 7 ns Voltage scaling Range 1 70
OSC_IN high or low time tw(HSEH), tw(HSEL) 18 ns Voltage scaling Range 2 70
LSI oscillator start-up time tSU(LSI) 80 130 µs Specified by design, not tested in production 75
LSI frequency fLSI 31.04 32.96 kHz VDD = 3.0 V, TA = 30 °C 75
LSI frequency fLSI 29.5 34 kHz VDD = 1.62 V to 3.6 V, TA = -40 to 125 °C 75
LSI oscillator stabilization time tSTAB(LSI) 125 180 µs 5% of final frequency 75
LSI oscillator power consumption IDD(LSI) 110 180 nA Specified by design, not tested in production 75

CAD (KiCad official)

  • Symbol: STM32G071K8U6
  • Footprint: Package_DFN_QFN:UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
  • 3D model: UFQFPN-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.55 mm nominal UFQFPN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: stm32g071k8u6-etched.step / stm32g071k8u6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g071k8u6.step / stm32g071k8u6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (143 pp, sha256 a83ee1377da65257, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF