component
STM32G071K8U6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-32(5x5). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
7 files changed
+139−132
README.md+33−32@@ -8,38 +8,39 @@ STM32G071K8U6 from STMicroelectronics, in a UFQFPN-32(5x5). Pinout and pin descr | Pin | Name | Type | Function | |---|---|---|---|-| 1 | PB9 | bidirectional | Fm+-capable 5 V-tolerant (FT_f) I/O with alternate functions including I2C1_SDA, USART3_RX, SPI2_NSS and IR_OUT. |-| 2 | PC14-OSC32_IN | bidirectional | 5 V-tolerant I/O supplied through the RTC-domain power switch, so it sinks/sources at most 3 mA in total with output speed limited to 2 MHz at 30 pF and must not drive loads as a current source; it also serves as the LSE oscillator input OSC32_IN. |-| 3 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant I/O supplied through the RTC-domain power switch (3 mA total sink/source limit, 2 MHz max output speed at 30 pF) that also serves as the LSE oscillator output OSC32_OUT. |-| 4 | VDD/VDDA | power_in | Main supply and analog supply pin: VDD = 1.7 V to 3.6 V, while VDDA ranges from 1.62 V (ADC and COMP), 1.8 V (DAC) or 2.4 V (VREFBUF) up to 3.6 V. |-| 5 | VSS/VSSA | power_in | Ground pin for the digital supply (VSS) and analog supply (VSSA); all device voltages are referenced to VSS. |-| 6 | PF2-NRST | bidirectional | Active-low reset pin with embedded weak pull-up (25 to 55 kΩ) and RST input levels (VIL max 0.3×VDDIO1, VIH min 0.7×VDDIO1); it operates as a 5 V-tolerant FT GPIO (PF2) when configured as GPIO. |-| 7 | PA0 | bidirectional | 5 V-tolerant analog-switch I/O (FT_a) that can also be used as ADC_IN0, COMP1_INM, TAMP_IN2 and WKUP1 wakeup input. |-| 8 | PA1 | bidirectional | 5 V-tolerant analog-switch I/O (FT_a) that can also be used as ADC_IN1 and COMP1_INP, with alternate functions including SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK and I2C1_SMBA. |-| 9 | PA2 | bidirectional | 5 V-tolerant analog-switch I/O (FT_a) that can also be used as ADC_IN2, COMP2_INM, WKUP4 and LSCO, with alternate functions including USART2_TX and LPUART1_TX. |-| 10 | PA3 | bidirectional | 5 V-tolerant analog-switch I/O (FT_a) that can also be used as ADC_IN3 and COMP2_INP, with alternate functions including USART2_RX, SPI2_MISO and LPUART1_RX. |-| 11 | PA4 | bidirectional | 3.6 V-tolerant analog-switch I/O (TT_a) that can also be used as ADC_IN4, DAC_OUT1, TAMP_IN1, RTC_TS, RTC_OUT1 and WKUP2. |-| 12 | PA5 | bidirectional | 3.6 V-tolerant analog-switch I/O (TT_a) that can also be used as ADC_IN5 and DAC_OUT2, with alternate functions including SPI1_SCK/I2S1_CK, CEC and USART3_TX. |-| 13 | PA6 | bidirectional | 5 V-tolerant analog-switch I/O (FT_a) that can also be used as ADC_IN6, with alternate functions including SPI1_MISO/I2S1_MCK, TIM1_BKIN and COMP1_OUT. |-| 14 | PA7 | bidirectional | 5 V-tolerant analog-switch I/O (FT_a) that can also be used as ADC_IN7, with alternate functions including SPI1_MOSI/I2S1_SD, TIM1_CH1N and COMP2_OUT. |-| 15 | PB0 | bidirectional | 5 V-tolerant analog-switch I/O (FT_a) that can also be used as ADC_IN8, with alternate functions including SPI1_NSS/I2S1_WS, USART3_RX, LPTIM1_OUT and COMP1_OUT. |-| 16 | PB1 | bidirectional | 5 V-tolerant analog-switch I/O (FT_a) that can also be used as ADC_IN9 and COMP1_INM, with alternate functions including TIM14_CH1, USART3_RTS_DE_CK and LPUART1_RTS_DE. |-| 17 | PB15 | bidirectional | 5 V-tolerant I/O with USB Type-C capability (FT_c) that can also be used as UCPD1_CC2 and RTC_REFIN; upon reset a pull-down may be present depending on the level on PB0/PA10 (strobe UCPDx_STROBE in SYSCFG_CFGR1 to disable it). |-| 18 | PA8 | bidirectional | 5 V-tolerant USB Type-C capable I/O (FT_c) that can also be used as UCPD1_CC1, with alternate functions including MCO, SPI2_NSS, TIM1_CH1 and LPTIM2_OUT; upon reset a pull-down may be present depending on the level on PA9/PC6. |-| 19 | PA9 | bidirectional | 5 V-tolerant Fm+-capable USB Type-C dead-battery I/O (FT_fd) that can also be used as UCPD1_DBCC1, with alternate functions including USART1_TX, I2C1_SCL and TIM15_BKIN; it can be remapped in place of PA11 via SYSCFG_CFGR1. |-| 20 | PC6 | bidirectional | 5 V-tolerant I/O (FT) with alternate functions including UCPD1_FRSTX, TIM3_CH1 and TIM2_CH3. |-| 21 | PA10 | bidirectional | 5 V-tolerant Fm+-capable USB Type-C dead-battery I/O (FT_fd) that can also be used as UCPD1_DBCC2, with alternate functions including USART1_RX, I2C1_SDA and TIM17_BKIN; it can be remapped in place of PA12 via SYSCFG_CFGR1. |-| 22 | PA11 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) printed as PA11 [PA9], with alternate functions including USART1_CTS, TIM1_CH4, I2C2_SCL and COMP1_OUT; it can be remapped in place of PA9 via SYSCFG_CFGR1. |-| 23 | PA12 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) printed as PA12 [PA10], with alternate functions including USART1_RTS_DE_CK, TIM1_ETR, I2C2_SDA and COMP2_OUT; it can be remapped in place of PA10 via SYSCFG_CFGR1. |-| 24 | PA13 | bidirectional | 5 V-tolerant I/O (FT) that is configured as SWDIO after reset with an internal pull-up active, with alternate functions including IR_OUT and EVENTOUT. |-| 25 | PA14-BOOT0 | bidirectional | 5 V-tolerant I/O (FT) that is configured as SWCLK after reset with an internal pull-down active, and also serves as the BOOT0 boot-mode pin, with USART2_TX as an alternate function. |-| 26 | PD0 | bidirectional | 5 V-tolerant USB Type-C capable I/O (FT_c) that can also be used as UCPD2_CC1, with alternate functions including SPI2_NSS, TIM16_CH1 and EVENTOUT; upon reset a pull-down may be present depending on the level on PD1. |-| 27 | PD1 | bidirectional | 5 V-tolerant Fm+-capable USB Type-C dead-battery I/O (FT_d) that can also be used as UCPD2_DBCC1, with alternate functions including SPI2_SCK, TIM17_CH1 and EVENTOUT. |-| 28 | PD2 | bidirectional | 5 V-tolerant USB Type-C capable I/O (FT_c) that can also be used as UCPD2_CC2, with alternate functions including USART3_RTS_DE_CK, TIM3_ETR and TIM1_CH1N; upon reset a pull-down may be present depending on the level on PD3. |-| 29 | PD3 | bidirectional | 5 V-tolerant Fm+-capable USB Type-C dead-battery I/O (FT_d) that can also be used as UCPD2_DBCC2, with alternate functions including USART2_CTS, SPI2_MISO and TIM1_CH2N. |-| 30 | PB6 | bidirectional | 5 V-tolerant Fm+-capable analog-switch I/O (FT_fa) that can also be used as COMP2_INP, with alternate functions including I2C1_SCL, USART1_TX and LPTIM1_ETR. |-| 31 | PB7 | bidirectional | 5 V-tolerant Fm+-capable analog-switch I/O (FT_fa) that can also be used as COMP2_INM and PVD_IN, with alternate functions including I2C1_SDA, USART1_RX and LPTIM1_IN2. |-| 32 | PB8 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f) with alternate functions including I2C1_SCL, USART3_TX, TIM16_CH1, TIM15_BKIN and CEC. |+| 1 | PB9 | bidirectional | 5 V-tolerant FT_f I/O with Fm+ capability, with alternate functions including IR_OUT, UCPD2_FRSTX, TIM17_CH1, USART3_RX, SPI2_NSS, I2C1_SDA and EVENTOUT. |+| 2 | PC14-OSC32_IN | bidirectional | FT I/O supplied through the power switch, sinking only a limited current (3 mA), so output speed must not exceed 2 MHz at 30 pF and it must not source current such as driving an LED; it also serves as the OSC32_IN oscillator input. |+| 3 | PC15-OSC32_OUT | bidirectional | FT I/O supplied through the power switch, sinking only a limited current (3 mA), so output speed must not exceed 2 MHz at 30 pF and it must not source current such as driving an LED; it also serves as the OSC32_OUT oscillator output. |+| 4 | VDD/VDDA | power_in | Main supply pin for the device and the analog supplies, operating from 1.7 V to 3.6 V. |+| 5 | VSS/VSSA | power_in | Ground pin for the digital and analog supply domains. |+| 6 | PF2-NRST | bidirectional | Active-low reset pin with an embedded weak pull-up resistor, operating as an FT I/O when configured as GPIO. |+| 7 | PA0 | bidirectional | FT_a I/O that also provides ADC input channel 0, COMP1 inverting input, and WKUP1 wakeup function. |+| 8 | PA1 | bidirectional | FT_a I/O that also provides ADC input channel 1 and COMP1 non-inverting input. |+| 9 | PA2 | bidirectional | FT_a I/O that also provides ADC input channel 2, COMP2 inverting input, WKUP4 and LSCO. |+| 10 | PA3 | bidirectional | FT_a I/O that also provides ADC input channel 3 and COMP2 non-inverting input. |+| 11 | PA4 | bidirectional | TT_a I/O (3.6 V tolerant) that also provides ADC input channel 4, DAC_OUT1 and RTC_OUT2. |+| 12 | PA5 | bidirectional | TT_a I/O (3.6 V tolerant) that also provides ADC input channel 5 and DAC_OUT2. |+| 13 | PA6 | bidirectional | FT_a I/O that also provides ADC input channel 6 and COMP1_OUT alternate function. |+| 14 | PA7 | bidirectional | FT_a I/O that also provides ADC input channel 7 and COMP2_OUT alternate function. |+| 15 | PB0 | bidirectional | FT_a I/O that also provides ADC input channel 8 and COMP1_OUT alternate function. |+| 16 | PB1 | bidirectional | FT_a I/O that also provides ADC input channel 9 and COMP1 inverting input. |+| 17 | PB2 | bidirectional | FT_a I/O that also provides ADC input channel 10 and COMP1 non-inverting input. |+| 18 | PA8 | bidirectional | FT_c I/O with USB Type-C PD capability, also providing MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT and UCPD1_CC1; a pull-down may be present at reset. |+| 19 | PA9 | bidirectional | FT_fd I/O with Fm+ capability and USB Type-C PD dead-battery function, also providing MCO, USART1_TX, TIM1_CH2, I2C1_SCL and UCPD1_DBCC1. |+| 20 | PC6 | bidirectional | FT I/O that also provides UCPD1_FRSTX, TIM3_CH1 and TIM2_CH3 alternate functions. |+| 21 | PA10 | bidirectional | FT_fd I/O with Fm+ capability and USB Type-C PD dead-battery function, also providing SPI2_MOSI, USART1_RX, TIM1_CH3, I2C1_SDA and UCPD1_DBCC2. |+| 22 | PA11 [PA9] | bidirectional | FT_f I/O with Fm+ capability that can be remapped in place of PA9 via SYSCFG_CFGR1, also providing USART1_CTS, TIM1_CH4, I2C2_SCL and COMP1_OUT. |+| 23 | PA12 [PA10] | bidirectional | FT_f I/O with Fm+ capability that can be remapped in place of PA10 via SYSCFG_CFGR1, also providing SPI1_MOSI, USART1_RTS_DE_CK, TIM1_ETR, I2C2_SDA and COMP2_OUT. |+| 24 | PA13 | bidirectional | FT I/O that is configured as the SWDIO debug function upon reset, with an internal pull-up enabled, and also provides IR_OUT and EVENTOUT. |+| 25 | PA14-BOOT0 | bidirectional | FT I/O that is configured as the SWCLK debug function upon reset with an internal pull-down enabled, and also serves as the BOOT0 boot pin. |+| 26 | PA15 | bidirectional | FT I/O that also provides SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, USART4_RTS_DE_CK, USART3_RTS_DE_CK and EVENTOUT. |+| 27 | PB3 | bidirectional | FT_a I/O that also provides SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK and EVENTOUT alternate functions, plus the COMP2 inverting input. |+| 28 | PB4 | bidirectional | FT_a I/O that also provides SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN and EVENTOUT alternate functions, plus the COMP2 non-inverting input. |+| 29 | PB5 | bidirectional | FT I/O that also provides SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1, I2C1_SMBA and COMP2_OUT alternate functions, plus the WKUP6 wakeup function. |+| 30 | PB6 | bidirectional | FT_fa I/O with Fm+ capability that also provides USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, EVENTOUT and the COMP2 non-inverting input. |+| 31 | PB7 | bidirectional | FT_fa I/O with Fm+ capability that also provides USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, the COMP2 inverting input and PVD_IN. |+| 32 | PB8 | bidirectional | FT_f I/O with Fm+ capability that also provides CEC, SPI2_SCK, TIM16_CH1, USART3_TX, TIM15_BKIN, I2C1_SCL and EVENTOUT. |+| 33 | EP | passive | Exposed pad (ST Figure 6 labels it Exposed pad); named EP as on the other STM32 UFQFPN32 pages. | ## Key specifications
package.json+2−2@@ -1,6 +1,6 @@ { "slug": "stm32g071k8u6",- "version": "0.1.0",+ "version": "0.1.1", "type": "component", "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-32(5x5). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.", "tags": [@@ -100,7 +100,7 @@ "number": "6", "name": "PF2-NRST", "type": "bidirectional",- "description": "Active-low reset pin with embedded weak pull-up (25 to 55 kΩ) and RST input levels (VIL max 0.3×VDDIO1, VIH min 0.7×VDDIO1); it operates as a 5 V-tolerant FT GPIO (PF2) when configured as GPIO."+ "description": "Active-low reset pin with embedded weak pull-up (25 to 55 k\u03a9) and RST input levels (VIL max 0.3\u00d7VDDIO1, VIH min 0.7\u00d7VDDIO1); it operates as a 5 V-tolerant FT GPIO (PF2) when configured as GPIO." }, { "number": "7",
page.json+4−4@@ -4,7 +4,7 @@ "slug": "stm32g071k8u6", "title": "STM32G071K8U6", "brief": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-32(5x5). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.1.1", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -1091,7 +1091,7 @@ "stm32g071k8u6-hero.overlay.json", "stm32g071k8u6-etched.glb" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-32(5x5). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "org": "adom" }
stm32g071k8u6-hero.glb⋯ 1 unchanged line ⋯
stm32g071k8u6-hero.overlay.json+8−8@@ -74,7 +74,7 @@ "footprint": "stm32g071k8u6.kicad_mod", "footprint_sha256": "16cf169e4f88dc2b16b7fced682500765995e61866aaeed377c5dc3c79f31a4b", "pins": "page.json component.pins",- "pins_sha256": "204d3c49beb6cb21d9459d9174912271b1cbe34962bd1230dd1777040e4b18d8"+ "pins_sha256": "052d8dcca788978610853d28d630a14db8f9c26c05d6809a9056dcefc3981686" }, "generator": "adom-wiki 1.8.11 (component_hero)", "labels": [@@ -224,7 +224,7 @@ }, { "pad": "17",- "text": "PB15",+ "text": "PB2", "x": 2.975, "y": 1.75, "align": "left",@@ -269,7 +269,7 @@ }, { "pad": "22",- "text": "PA11",+ "text": "PA11 [PA9]", "x": 2.975, "y": -0.75, "align": "left",@@ -278,7 +278,7 @@ }, { "pad": "23",- "text": "PA12",+ "text": "PA12 [PA10]", "x": 2.975, "y": -1.25, "align": "left",@@ -305,7 +305,7 @@ }, { "pad": "26",- "text": "PD0",+ "text": "PA15", "x": 1.25, "y": -2.975, "align": "left",@@ -314,7 +314,7 @@ }, { "pad": "27",- "text": "PD1",+ "text": "PB3", "x": 0.75, "y": -2.975, "align": "left",@@ -323,7 +323,7 @@ }, { "pad": "28",- "text": "PD2",+ "text": "PB4", "x": 0.25, "y": -2.975, "align": "left",@@ -332,7 +332,7 @@ }, { "pad": "29",- "text": "PD3",+ "text": "PB5", "x": -0.25, "y": -2.975, "align": "left",
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stm32g071k8u6.lbr+45−43@@ -114,44 +114,45 @@ <symbols> <symbol name="STM32G071K8U6"> <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-32(5x5). Pinout checked against ST's open pin data</description>- <wire x1="-12.7" y1="20.32" x2="12.7" y2="20.32" width="0.254" layer="94"/>- <wire x1="12.7" y1="20.32" x2="12.7" y2="-22.86" width="0.254" layer="94"/>+ <wire x1="-12.7" y1="22.86" x2="12.7" y2="22.86" width="0.254" layer="94"/>+ <wire x1="12.7" y1="22.86" x2="12.7" y2="-22.86" width="0.254" layer="94"/> <wire x1="12.7" y1="-22.86" x2="-12.7" y2="-22.86" width="0.254" layer="94"/>- <wire x1="-12.7" y1="-22.86" x2="-12.7" y2="20.32" width="0.254" layer="94"/>- <text x="0.0000" y="22.8600" size="1.27" layer="95" align="center">>NAME</text>+ <wire x1="-12.7" y1="-22.86" x2="-12.7" y2="22.86" width="0.254" layer="94"/>+ <text x="0.0000" y="25.4000" size="1.27" layer="95" align="center">>NAME</text> <text x="0.0000" y="-25.4000" size="1.27" layer="96" align="center">>VALUE</text>- <pin name="PB9" x="-17.78" y="17.78" length="middle" direction="io"/>- <pin name="PC14-OSC32_IN" x="-17.78" y="15.24" length="middle" direction="io"/>- <pin name="PC15-OSC32_OUT" x="-17.78" y="12.7" length="middle" direction="io"/>- <pin name="VDD/VDDA" x="-17.78" y="10.16" length="middle" direction="pwr"/>- <pin name="VSS/VSSA" x="-17.78" y="7.62" length="middle" direction="pwr"/>- <pin name="PF2-NRST" x="-17.78" y="5.08" length="middle" direction="io"/>- <pin name="PA0" x="-17.78" y="2.54" length="middle" direction="io"/>- <pin name="PA1" x="-17.78" y="0" length="middle" direction="io"/>- <pin name="PA2" x="-17.78" y="-2.54" length="middle" direction="io"/>- <pin name="PA3" x="-17.78" y="-5.08" length="middle" direction="io"/>- <pin name="PA4" x="-17.78" y="-7.62" length="middle" direction="io"/>- <pin name="PA5" x="-17.78" y="-10.16" length="middle" direction="io"/>- <pin name="PA6" x="-17.78" y="-12.7" length="middle" direction="io"/>- <pin name="PA7" x="-17.78" y="-15.24" length="middle" direction="io"/>- <pin name="PB0" x="-17.78" y="-17.78" length="middle" direction="io"/>- <pin name="PB1" x="-17.78" y="-20.32" length="middle" direction="io"/>- <pin name="PB8" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/>- <pin name="PB7" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>- <pin name="PB6" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>- <pin name="PD3" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>- <pin name="PD2" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>- <pin name="PD1" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>- <pin name="PD0" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>- <pin name="PA14-BOOT0" x="17.78" y="0" length="middle" direction="io" rot="R180"/>- <pin name="PA13" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>- <pin name="PA12" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>- <pin name="PA11" x="17.78" y="-7.62" length="middle" direction="io" rot="R180"/>- <pin name="PA10" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>- <pin name="PC6" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>- <pin name="PA9" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>- <pin name="PA8" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>- <pin name="PB15" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PB9" x="-17.78" y="20.32" length="middle" direction="io"/>+ <pin name="PC14-OSC32_IN" x="-17.78" y="17.78" length="middle" direction="io"/>+ <pin name="PC15-OSC32_OUT" x="-17.78" y="15.24" length="middle" direction="io"/>+ <pin name="VDD/VDDA" x="-17.78" y="12.7" length="middle" direction="pwr"/>+ <pin name="VSS/VSSA" x="-17.78" y="10.16" length="middle" direction="pwr"/>+ <pin name="PF2-NRST" x="-17.78" y="7.62" length="middle" direction="io"/>+ <pin name="PA0" x="-17.78" y="5.08" length="middle" direction="io"/>+ <pin name="PA1" x="-17.78" y="2.54" length="middle" direction="io"/>+ <pin name="PA2" x="-17.78" y="0" length="middle" direction="io"/>+ <pin name="PA3" x="-17.78" y="-2.54" length="middle" direction="io"/>+ <pin name="PA4" x="-17.78" y="-5.08" length="middle" direction="io"/>+ <pin name="PA5" x="-17.78" y="-7.62" length="middle" direction="io"/>+ <pin name="PA6" x="-17.78" y="-10.16" length="middle" direction="io"/>+ <pin name="PA7" x="-17.78" y="-12.7" length="middle" direction="io"/>+ <pin name="PB0" x="-17.78" y="-15.24" length="middle" direction="io"/>+ <pin name="PB1" x="-17.78" y="-17.78" length="middle" direction="io"/>+ <pin name="PB2" x="-17.78" y="-20.32" length="middle" direction="io"/>+ <pin name="EP" x="17.78" y="17.78" length="middle" direction="pas" rot="R180"/>+ <pin name="PB8" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PB7" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PB6" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PB5" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+ <pin name="PB4" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="PB3" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="PA15" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+ <pin name="PA14-BOOT0" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>+ <pin name="PA13" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>+ <pin name="PA12_PA10" x="17.78" y="-7.62" length="middle" direction="io" rot="R180"/>+ <pin name="PA11_PA9" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PA10" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PC6" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PA9" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PA8" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/> </symbol> </symbols> <devicesets>@@ -179,22 +180,23 @@ <connect gate="G$1" pin="PA7" pad="14"/> <connect gate="G$1" pin="PB0" pad="15"/> <connect gate="G$1" pin="PB1" pad="16"/>+ <connect gate="G$1" pin="PB2" pad="17"/>+ <connect gate="G$1" pin="EP" pad="33"/> <connect gate="G$1" pin="PB8" pad="32"/> <connect gate="G$1" pin="PB7" pad="31"/> <connect gate="G$1" pin="PB6" pad="30"/>- <connect gate="G$1" pin="PD3" pad="29"/>- <connect gate="G$1" pin="PD2" pad="28"/>- <connect gate="G$1" pin="PD1" pad="27"/>- <connect gate="G$1" pin="PD0" pad="26"/>+ <connect gate="G$1" pin="PB5" pad="29"/>+ <connect gate="G$1" pin="PB4" pad="28"/>+ <connect gate="G$1" pin="PB3" pad="27"/>+ <connect gate="G$1" pin="PA15" pad="26"/> <connect gate="G$1" pin="PA14-BOOT0" pad="25"/> <connect gate="G$1" pin="PA13" pad="24"/>- <connect gate="G$1" pin="PA12" pad="23"/>- <connect gate="G$1" pin="PA11" pad="22"/>+ <connect gate="G$1" pin="PA12_PA10" pad="23"/>+ <connect gate="G$1" pin="PA11_PA9" pad="22"/> <connect gate="G$1" pin="PA10" pad="21"/> <connect gate="G$1" pin="PC6" pad="20"/> <connect gate="G$1" pin="PA9" pad="19"/> <connect gate="G$1" pin="PA8" pad="18"/>- <connect gate="G$1" pin="PB15" pad="17"/> </connects> <technologies> <technology name="">