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STM32F401CCU6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f401ccu6
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3D Model

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Symbol & Footprint

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Contents

README

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STM32F401CCU6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32F401CCU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain supply, 1.65 V-3.6 V. Powers RTC, LSE, and backup registers when VDD is off.
2 PC13 bidirectional General-purpose 5 V-tolerant I/O. Supplied via the backup power switch (max sink 3 mA, 2 MHz / 30 pF limit). Alt functions: EVENTOUT; additional: RTC_TAMP1, RTC_OUT, RTC_TS.
3 PC14/OSC32_IN bidirectional GPIO (FT except in oscillator/analog mode) or low-speed 32.768 kHz LSE crystal input. Backup-domain I/O with limited drive.
4 PC15/OSC32_OUT bidirectional GPIO (FT except in oscillator/analog mode) or 32.768 kHz LSE crystal output. Backup-domain I/O.
5 PH0/OSC_IN bidirectional GPIO or main HSE crystal/clock input (4-26 MHz). FT except in oscillator/analog mode.
6 PH1/OSC_OUT bidirectional GPIO or main HSE crystal output. FT except in oscillator/analog mode.
7 NRST bidirectional Bidirectional device reset input/open-drain output with embedded weak pull-up (~40 kΩ). Active low.
8 VSSA/VREF- power_in Analog ground and negative ADC reference (tied together on this package). Connect to system ground.
9 VDDA/VREF+ power_in Analog supply and positive ADC reference (tied together on this package). 1.7 V-3.6 V. Decouple with 100 nF + 1 µF.
10 PA0-WKUP bidirectional GPIO (FT). Alt: USART2_CTS, TIM2_CH1/TIM2_ETR, TIM5_CH1, EVENTOUT. Additional: ADC1_IN0, WKUP (wake-up from Standby).
11 PA1 bidirectional GPIO (FT). Alt: USART2_RTS, TIM2_CH2, TIM5_CH2, EVENTOUT. Additional: ADC1_IN1.
12 PA2 bidirectional GPIO (FT). Alt: USART2_TX, TIM2_CH3, TIM5_CH3, TIM9_CH1, EVENTOUT. Additional: ADC1_IN2.
13 PA3 bidirectional GPIO (FT). Alt: USART2_RX, TIM2_CH4, TIM5_CH4, TIM9_CH2, EVENTOUT. Additional: ADC1_IN3.
14 PA4 bidirectional GPIO (FT). Alt: SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT. Additional: ADC1_IN4.
15 PA5 bidirectional GPIO (FT). Alt: SPI1_SCK, TIM2_CH1/TIM2_ETR, EVENTOUT. Additional: ADC1_IN5.
16 PA6 bidirectional GPIO (FT). Alt: SPI1_MISO, TIM1_BKIN, TIM3_CH1, EVENTOUT. Additional: ADC1_IN6.
17 PA7 bidirectional GPIO (FT). Alt: SPI1_MOSI, TIM1_CH1N, TIM3_CH2, EVENTOUT. Additional: ADC1_IN7.
18 PB0 bidirectional GPIO (FT). Alt: TIM1_CH2N, TIM3_CH3, EVENTOUT. Additional: ADC1_IN8.
19 PB1 bidirectional GPIO (FT). Alt: TIM1_CH3N, TIM3_CH4, EVENTOUT. Additional: ADC1_IN9.
20 PB2/BOOT1 bidirectional GPIO (FT). Alt: EVENTOUT. Additional: BOOT1 boot-mode selector (sampled at reset together with BOOT0).
21 PB10 bidirectional GPIO (FT). Alt: SPI2_SCK/I2S2_CK, I2C2_SCL, TIM2_CH3, EVENTOUT.
22 VCAP_1 passive Internal 1.2 V regulator decoupling pin. Connect a 2.2 µF ceramic to VSS (see datasheet Table 15).
23 VSS power_in Digital ground.
24 VDD power_in Digital I/O and core supply, 1.7 V-3.6 V. Decouple with 100 nF per pin plus a bulk cap.
25 PB12 bidirectional GPIO (FT). Alt: SPI2_NSS/I2S2_WS, I2C2_SMBA, TIM1_BKIN, EVENTOUT.
26 PB13 bidirectional GPIO (FT). Alt: SPI2_SCK/I2S2_CK, TIM1_CH1N, EVENTOUT.
27 PB14 bidirectional GPIO (FT). Alt: SPI2_MISO, I2S2ext_SD, TIM1_CH2N, EVENTOUT.
28 PB15 bidirectional GPIO (FT). Alt: SPI2_MOSI/I2S2_SD, TIM1_CH3N, EVENTOUT. Additional: RTC_REFIN.
29 PA8 bidirectional GPIO (FT). Alt: I2C3_SCL, USART1_CK, TIM1_CH1, OTG_FS_SOF, MCO_1, EVENTOUT.
30 PA9 bidirectional GPIO (FT). Alt: I2C3_SMBA, USART1_TX, TIM1_CH2, EVENTOUT. Additional: OTG_FS_VBUS (USB VBUS sense).
31 PA10 bidirectional GPIO (FT). Alt: USART1_RX, TIM1_CH3, OTG_FS_ID, EVENTOUT. Serves as USB OTG ID pin.
32 PA11 bidirectional GPIO (FT). Alt: USART1_CTS, USART6_TX, TIM1_CH4, OTG_FS_DM (USB D−), EVENTOUT.
33 PA12 bidirectional GPIO (FT). Alt: USART1_RTS, USART6_RX, TIM1_ETR, OTG_FS_DP (USB D+), EVENTOUT.
34 PA13/JTMS-SWDIO bidirectional GPIO (FT). Alt: JTMS/SWDIO debug data. Default after reset: SWDIO with internal pull-up.
35 VSS power_in Digital ground.
36 VDD power_in Digital I/O and core supply, 1.7 V-3.6 V.
37 PA14/JTCK-SWCLK bidirectional GPIO (FT). Alt: JTCK/SWCLK debug clock. Default after reset: SWCLK with internal pull-down.
38 PA15/JTDI bidirectional GPIO (FT). Alt: JTDI, SPI1_NSS, SPI3_NSS/I2S3_WS, TIM2_CH1/TIM2_ETR, EVENTOUT. Default after reset: JTDI with pull-up.
39 PB3/JTDO-SWO bidirectional GPIO (FT). Alt: JTDO/SWO trace, SPI1_SCK, SPI3_SCK/I2S3_CK, I2C2_SDA, TIM2_CH2, EVENTOUT.
40 PB4/NJTRST bidirectional GPIO (FT). Alt: NJTRST, SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, TIM3_CH1, EVENTOUT. Default after reset: NJTRST with pull-up.
41 PB5 bidirectional GPIO (FT). Alt: SPI1_MOSI, SPI3_MOSI/I2S3_SD, I2C1_SMBA, TIM3_CH2, EVENTOUT.
42 PB6 bidirectional GPIO (FT). Alt: I2C1_SCL, USART1_TX, TIM4_CH1, EVENTOUT.
43 PB7 bidirectional GPIO (FT). Alt: I2C1_SDA, USART1_RX, TIM4_CH2, EVENTOUT.
44 BOOT0 input Boot-mode select input (dedicated BOOT0 pad). Also VPP for factory programming. Sampled at reset with BOOT1 to select main flash / system memory / SRAM boot.
45 PB8 bidirectional GPIO (FT). Alt: I2C1_SCL, TIM4_CH3, TIM10_CH1, SDIO_D4, EVENTOUT.
46 PB9 bidirectional GPIO (FT). Alt: SPI2_NSS/I2S2_WS, I2C1_SDA, TIM4_CH4, TIM11_CH1, SDIO_D5, EVENTOUT.
47 VSS power_in Digital ground.
48 VDD power_in Digital I/O and core supply, 1.7 V-3.6 V.

Key specifications

Parameter Value
Core Arm Cortex-M4
Max clock 84 MHz
Flash 256 kB
RAM 64 kB
I/O pins 36
ADC units 1
Supply 1.7 to 3.6 V
Temperature -40 to 85 C
ST status Active
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Ordering variants

Same part, different packaging or reel option.

  • STM32F401CCU6U
  • STM32F401CCU6Y
  • STM32F401CCU6R
  • STM32F401CCU6V
  • STM32F401CCU6H

CAD (KiCad official)

  • Symbol: STM32F401CCU6
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f401ccu6-etched.step / stm32f401ccu6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f401ccu6.step / stm32f401ccu6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (52 pp, sha256 9b9598e12e8fc850, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF