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STM32F205RCT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F205RCT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F205RCT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Battery supply for RTC, 20×32-bit backup registers, and optional 4 KB backup SRAM; stays powered when VDD is removed. |
| 2 | PC13 | bidirectional | 5 V-tolerant I/O supplied through power switch; output limited to ≤2 MHz and ≤30 pF load (max 3 mA switch current); alternate function RTC_AF1 after first backup-domain power-up. |
| 3 | PC14-OSC32_IN | bidirectional | 5 V-tolerant I/O or 32.768 kHz crystal oscillator input (OSC32_IN); output limited to ≤2 MHz / ≤30 pF; not 5 V-tolerant in oscillator mode. |
| 4 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant I/O or 32.768 kHz crystal oscillator output (OSC32_OUT); output limited to ≤2 MHz / ≤30 pF; not 5 V-tolerant in oscillator mode. |
| 5 | PH0-OSC_IN | bidirectional | 5 V-tolerant I/O or 4-26 MHz high-speed external crystal oscillator input (OSC_IN); not 5 V-tolerant in oscillator mode. |
| 6 | PH1-OSC_OUT | bidirectional | 5 V-tolerant I/O or 4-26 MHz high-speed external crystal oscillator output (OSC_OUT); not 5 V-tolerant in oscillator mode. |
| 7 | NRST | bidirectional | Bidirectional system reset pin with embedded weak pull-up resistor; active-low; filters glitches shorter than the minimum pulse width. |
| 8 | PC0 | bidirectional | 5 V-tolerant I/O with ADC123_IN10 analog input; alternate function OTG_HS_ULPI_STP. |
| 9 | PC1 | bidirectional | 5 V-tolerant I/O with ADC123_IN11 analog input; alternate function ETH_MDC. |
| 10 | PC2 | bidirectional | 5 V-tolerant I/O with ADC123_IN12 analog input; alternate functions SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2. |
| 11 | PC3 | bidirectional | 5 V-tolerant I/O with ADC123_IN13 analog input; alternate functions SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK. |
| 12 | VSSA | power_in | Analog ground reference for ADC, DAC, and embedded reference voltage; must be tied to VSS. |
| 13 | VDDA | power_in | Analog supply for ADC, DAC, reset block, and RC oscillators; 1.8-3.6 V. |
| 14 | PA0-WKUP | bidirectional | 5 V-tolerant I/O with Standby wake-up (WKUP) and ADC123_IN0 analog input; alternate functions USART2_CTS, UART4_TX, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, ETH_MII_CRS. |
| 15 | PA1 | bidirectional | 5 V-tolerant I/O with ADC123_IN1 analog input; alternate functions USART2_RTS, UART4_RX, ETH_RMII_REF_CLK/ETH_MII_RX_CLK, TIM5_CH2, TIM2_CH2. |
| 16 | PA2 | bidirectional | 5 V-tolerant I/O with ADC123_IN2 analog input; alternate functions USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO. |
| 17 | PA3 | bidirectional | 5 V-tolerant I/O with ADC123_IN3 analog input; alternate functions USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL. |
| 18 | VSS | power_in | Digital ground supply; 0 V reference for all digital circuitry. |
| 19 | VDD | power_in | Main digital supply; 1.8-3.6 V for I/O buffers and digital core. |
| 20 | PA4 | bidirectional | 3.3 V-tolerant I/O (TTa) with ADC12_IN4 analog input and DAC_OUT1 analog output; alternate functions SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF. |
| 21 | PA5 | bidirectional | 3.3 V-tolerant I/O (TTa) with ADC12_IN5 analog input and DAC_OUT2 analog output; alternate functions SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N. |
| 22 | PA6 | bidirectional | 5 V-tolerant I/O with ADC12_IN6 analog input; alternate functions SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN. |
| 23 | PA7 | bidirectional | 5 V-tolerant I/O with ADC12_IN7 analog input; alternate functions SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV/ETH_RMII_CRS_DV, TIM1_CH1N. |
| 24 | PC4 | bidirectional | 5 V-tolerant I/O with ADC12_IN14 analog input; alternate functions ETH_RMII_RXD0, ETH_MII_RXD0. |
| 25 | PC5 | bidirectional | 5 V-tolerant I/O with ADC12_IN15 analog input; alternate functions ETH_RMII_RXD1, ETH_MII_RXD1. |
| 26 | PB0 | bidirectional | 5 V-tolerant I/O with ADC12_IN8 analog input; alternate functions TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N. |
| 27 | PB1 | bidirectional | 5 V-tolerant I/O with ADC12_IN9 analog input; alternate functions TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N. |
| 28 | PB2 | bidirectional | 5 V-tolerant I/O; used with BOOT0 to select boot mode at reset (BOOT1 function). |
| 29 | PB10 | bidirectional | 5 V-tolerant I/O; alternate functions SPI2_SCK/I2S2_SCK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TIM2_CH3. |
| 30 | PB11 | bidirectional | 5 V-tolerant I/O; alternate functions I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_RMII_TX_EN/ETH_MII_TX_EN, TIM2_CH4. |
| 31 | VCAP_1 | passive | Internal core-domain LDO output 1; requires 2.2 µF external decoupling capacitor to VSS; must not be connected to VDD. |
| 32 | VDD | power_in | Main digital supply; 1.8-3.6 V for I/O buffers and digital core. |
| 33 | PB12 | bidirectional | 5 V-tolerant I/O; alternate functions SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0/ETH_MII_TXD0, OTG_HS_ID. |
| 34 | PB13 | bidirectional | 5 V-tolerant I/O with OTG_HS_VBUS monitor function; alternate functions SPI2_SCK/I2S2_SCK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6, ETH_RMII_TXD1/ETH_MII_TXD1. |
| 35 | PB14 | bidirectional | 5 V-tolerant I/O; alternate functions SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N. |
| 36 | PB15 | bidirectional | 5 V-tolerant I/O; alternate functions SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, OTG_HS_DP, RTC_50Hz. |
| 37 | PC6 | bidirectional | 5 V-tolerant I/O; alternate functions I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0, TIM3_CH1. |
| 38 | PC7 | bidirectional | 5 V-tolerant I/O; alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1, TIM3_CH2. |
| 39 | PC8 | bidirectional | 5 V-tolerant I/O; alternate functions TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2. |
| 40 | PC9 | bidirectional | 5 V-tolerant I/O; alternate functions MCO2, I2S2_CKIN/I2S3_CKIN, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3, TIM3_CH4. |
| 41 | PA8 | bidirectional | 5 V-tolerant I/O; alternate functions MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF. |
| 42 | PA9 | bidirectional | 5 V-tolerant I/O with OTG_FS_VBUS monitor function; alternate functions USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0. |
| 43 | PA10 | bidirectional | 5 V-tolerant I/O; alternate functions USART1_RX, TIM1_CH3, OTG_FS_ID, DCMI_D1. |
| 44 | PA11 | bidirectional | 5 V-tolerant I/O; alternate functions USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM. |
| 45 | PA12 | bidirectional | 5 V-tolerant I/O; alternate functions USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP. |
| 46 | PA13 | bidirectional | 5 V-tolerant I/O; default function JTAG TMS / SWD data I/O (JTMS-SWDIO) active after reset. |
| 47 | VCAP_2 | passive | Internal core-domain LDO output 2; requires 2.2 µF external decoupling capacitor to VSS; must not be connected to VDD. |
| 48 | VDD | power_in | Main digital supply; 1.8-3.6 V for I/O buffers and digital core. |
| 49 | PA14 | bidirectional | 5 V-tolerant I/O; default function JTAG TCK / SWD clock (JTCK-SWCLK) active after reset. |
| 50 | PA15 | bidirectional | 5 V-tolerant I/O; default function JTAG TDI (JTDI) active after reset; alternate functions SPI3_NSS/I2S3_WS, TIM2_CH1_ETR, SPI1_NSS. |
| 51 | PC10 | bidirectional | 5 V-tolerant I/O; alternate functions SPI3_SCK/I2S3_SCK, UART4_TX, SDIO_D2, DCMI_D8, USART3_TX. |
| 52 | PC11 | bidirectional | 5 V-tolerant I/O; alternate functions UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX. |
| 53 | PC12 | bidirectional | 5 V-tolerant I/O; alternate functions UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI/I2S3_SD, USART3_CK. |
| 54 | PD2 | bidirectional | 5 V-tolerant I/O; alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11. |
| 55 | PB3 | bidirectional | 5 V-tolerant I/O; default function JTAG TDO / Trace SWO (JTDO/TRACESWO) active after reset; alternate functions SPI3_SCK/I2S3_SCK, TIM2_CH2, SPI1_SCK. |
| 56 | PB4 | bidirectional | 5 V-tolerant I/O; default function NJTRST active after reset; alternate functions SPI3_MISO, TIM3_CH1, SPI1_MISO. |
| 57 | PB5 | bidirectional | 5 V-tolerant I/O; alternate functions I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI/I2S3_SD, DCMI_D10. |
| 58 | PB6 | bidirectional | 5 V-tolerant I/O; alternate functions I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5, USART1_TX. |
| 59 | PB7 | bidirectional | 5 V-tolerant I/O; alternate functions I2C1_SDA, FSMC_NL/NADV, DCMI_VSYNC, USART1_RX, TIM4_CH2. |
| 60 | BOOT0 | input | Dedicated BOOT0 input (type I, structure B) for selecting boot mode at reset in combination with BOOT1/PB2; also serves as VPP for Flash programming. |
| 61 | PB8 | bidirectional | 5 V-tolerant I/O; alternate functions TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL, CAN1_RX. |
| 62 | PB9 | bidirectional | 5 V-tolerant I/O; alternate functions SPI2_NSS/I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA, CAN1_TX. |
| 63 | VSS | power_in | Digital ground supply; 0 V reference for all digital circuitry. |
| 64 | VDD | power_in | Main digital supply; 1.8-3.6 V for I/O buffers and digital core. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F205RCT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32f205rct6-etched.step/stm32f205rct6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f205rct6.step/stm32f205rct6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (179 pp, sha256
6ffebd41462b5c10, retrieved 2026-09-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).