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STM32F105R8T6TR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F105R8T6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F105R8T6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup supply (1.8 to 3.6 V) for the RTC, external 32 kHz oscillator and backup registers when VDD is not present.
2 PC13-TAMPER-RTC bidirectional GPIO PC13 or TAMPER-RTC, supplied through the power switch so output use is limited to 2 MHz mode with max 30 pF load and only one such pin as output at a time.
3 PC14-OSC32_IN bidirectional GPIO PC14 or 32 kHz oscillator input OSC32_IN, supplied through the power switch with output use limited to 2 MHz, 30 pF max, one pin at a time.
4 PC15-OSC32_OUT bidirectional GPIO PC15 or 32 kHz oscillator output OSC32_OUT, supplied through the power switch with output use limited to 2 MHz, 30 pF max, one pin at a time.
5 OSC_IN input Main 3-25 MHz oscillator input after reset; PD0 can be remapped onto this pin by software.
6 OSC_OUT output Main 3-25 MHz oscillator output after reset; PD1 can be remapped onto this pin by software.
7 NRST bidirectional Device reset input/output, main function NRST after reset.
8 PC0 bidirectional General-purpose I/O PC0 with alternate function ADC12_IN10.
9 PC1 bidirectional General-purpose I/O PC1 with alternate functions ADC12_IN11 and ETH_MII_MDC/ETH_RMII_MDC.
10 PC2 bidirectional General-purpose I/O PC2 with alternate functions ADC12_IN12 and ETH_MII_TXD2.
11 PC3 bidirectional General-purpose I/O PC3 with alternate functions ADC12_IN13 and ETH_MII_TX_CLK.
12 VSSA power_in Analog ground for ADC, reset blocks, RCs and PLL; must be connected to VSS.
13 VDDA power_in Analog supply 2.0 to 3.6 V (minimum 2.4 V when the ADC is used); must be connected to VDD.
14 PA0-WKUP bidirectional General-purpose I/O PA0 with WKUP, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR, TIM5_CH1 and ETH_MII_CRS_WKUP functions.
15 PA1 bidirectional General-purpose I/O PA1 with USART2_RTS, ADC12_IN1, TIM5_CH2, TIM2_CH2, ETH_MII_RX_CLK/ETH_RMII_REF_CLK functions.
16 PA2 bidirectional General-purpose I/O PA2 with USART2_TX, TIM5_CH3, ADC12_IN2, TIM2_CH3, ETH_MII_MDIO/ETH_RMII_MDIO functions.
17 PA3 bidirectional General-purpose I/O PA3 with USART2_RX, TIM5_CH4, ADC12_IN3, TIM2_CH4, ETH_MII_COL functions.
18 VSS_4 power_in Digital ground supply pin VSS_4.
19 VDD_4 power_in Digital supply pin VDD_4 for I/Os and internal regulator, 2.0 to 3.6 V.
20 PA4 bidirectional General-purpose I/O PA4 with SPI1_NSS, DAC_OUT1, USART2_CK, ADC12_IN4; remap SPI3_NSS/I2S3_WS.
21 PA5 bidirectional General-purpose I/O PA5 with SPI1_SCK, DAC_OUT2 and ADC12_IN5.
22 PA6 bidirectional General-purpose I/O PA6 with SPI1_MISO, ADC12_IN6, TIM3_CH1; remap TIM1_BKIN.
23 PA7 bidirectional General-purpose I/O PA7 with SPI1_MOSI, ADC12_IN7, TIM3_CH2, ETH_MII_RX_DV/ETH_RMII_CRS_DV; remap TIM1_CH1N.
24 PC4 bidirectional General-purpose I/O PC4 with ADC12_IN14 and ETH_MII_RXD0/ETH_RMII_RXD0.
25 PC5 bidirectional General-purpose I/O PC5 with ADC12_IN15 and ETH_MII_RXD1/ETH_RMII_RXD1.
26 PB0 bidirectional General-purpose I/O PB0 with ADC12_IN8, TIM3_CH3, ETH_MII_RXD2; remap TIM1_CH2N.
27 PB1 bidirectional General-purpose I/O PB1 with ADC12_IN9, TIM3_CH4, ETH_MII_RXD3; remap TIM1_CH3N.
28 PB2/BOOT1 bidirectional 5 V-tolerant I/O PB2 that also serves as the BOOT1 boot mode selection pin.
29 PB10 bidirectional 5 V-tolerant I/O PB10 with I2C2_SCL, USART3_TX, ETH_MII_RX_ER; remap TIM2_CH3.
30 PB11 bidirectional 5 V-tolerant I/O PB11 with I2C2_SDA, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX_EN; remap TIM2_CH4.
31 VSS_1 power_in Digital ground supply pin VSS_1.
32 VDD_1 power_in Digital supply pin VDD_1 for I/Os and internal regulator, 2.0 to 3.6 V.
33 PB12 bidirectional 5 V-tolerant I/O PB12 with SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX and ETH_MII_TXD0/ETH_RMII_TXD0.
34 PB13 bidirectional 5 V-tolerant I/O PB13 with SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and ETH_MII_TXD1/ETH_RMII_TXD1.
35 PB14 bidirectional 5 V-tolerant I/O PB14 with SPI2_MISO, TIM1_CH2N and USART3_RTS.
36 PB15 bidirectional 5 V-tolerant I/O PB15 with SPI2_MOSI/I2S2_SD and TIM1_CH3N.
37 PC6 bidirectional 5 V-tolerant I/O PC6 with I2S2_MCK; remap TIM3_CH1.
38 PC7 bidirectional 5 V-tolerant I/O PC7 with I2S3_MCK; remap TIM3_CH2.
39 PC8 bidirectional 5 V-tolerant I/O PC8; remap TIM3_CH3.
40 PC9 bidirectional 5 V-tolerant I/O PC9; remap TIM3_CH4.
41 PA8 bidirectional 5 V-tolerant I/O PA8 with USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO.
42 PA9 bidirectional 5 V-tolerant I/O PA9 with USART1_TX, TIM1_CH2 and OTG_FS_VBUS.
43 PA10 bidirectional 5 V-tolerant I/O PA10 with USART1_RX, TIM1_CH3 and OTG_FS_ID.
44 PA11 bidirectional 5 V-tolerant I/O PA11 with USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM.
45 PA12 bidirectional 5 V-tolerant I/O PA12 with USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR.
46 PA13 bidirectional 5 V-tolerant pin that is JTMS-SWDIO after reset; PA13 is its remap function.
47 VSS_2 power_in Digital ground supply pin VSS_2.
48 VDD_2 power_in Digital supply pin VDD_2 for I/Os and internal regulator, 2.0 to 3.6 V.
49 PA14 bidirectional 5 V-tolerant pin that is JTCK-SWCLK after reset; PA14 is its remap function.
50 PA15 bidirectional 5 V-tolerant pin that is JTDI after reset, with SPI3_NSS/I2S3_WS; remap TIM2_CH1_ETR, PA15, SPI1_NSS.
51 PC10 bidirectional 5 V-tolerant I/O PC10 with UART4_TX; remap USART3_TX, SPI3_SCK/I2S3_CK.
52 PC11 bidirectional 5 V-tolerant I/O PC11 with UART4_RX; remap USART3_RX, SPI3_MISO.
53 PC12 bidirectional 5 V-tolerant I/O PC12 with UART5_TX; remap USART3_CK, SPI3_MOSI/I2S3_SD.
54 PD2 bidirectional 5 V-tolerant I/O PD2 with TIM3_ETR and UART5_RX.
55 PB3 bidirectional 5 V-tolerant pin that is JTDO after reset, with SPI3_SCK/I2S3_CK; remap PB3, TRACESWO, TIM2_CH2, SPI1_SCK.
56 PB4 bidirectional 5 V-tolerant pin that is NJTRST after reset, with SPI3_MISO; remap PB4, TIM3_CH1, SPI1_MISO.
57 PB5 bidirectional I/O PB5 with I2C1_SMBA, SPI3_MOSI/I2S3_SD, ETH_MII_PPS_OUT; remap TIM3_CH2, SPI1_MOSI, CAN2_RX.
58 PB6 bidirectional 5 V-tolerant I/O PB6 with I2C1_SCL and TIM4_CH1; remap USART1_TX, CAN2_TX.
59 PB7 bidirectional 5 V-tolerant I/O PB7 with I2C1_SDA and TIM4_CH2; remap USART1_RX.
60 BOOT0 input Boot mode selection input.
61 PB8 bidirectional 5 V-tolerant I/O PB8 with TIM4_CH3 and ETH_MII_TXD3; remap I2C1_SCL, CAN1_RX.
62 PB9 bidirectional 5 V-tolerant I/O PB9 with TIM4_CH4; remap I2C1_SDA, CAN1_TX.
63 VSS_3 power_in Digital ground supply pin VSS_3.
64 VDD_3 power_in Digital supply pin VDD_3 for I/Os and internal regulator, 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32F105R8T6TR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f105r8t6tr-etched.step / stm32f105r8t6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f105r8t6tr.step / stm32f105r8t6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (108 pp, sha256 ca4bad652e5eb36d, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF