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STM32F105R8T6TR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
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README.mdadded+100@@ -0,0 +1,100 @@+# STM32F105R8T6TR++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)++STM32F105R8T6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VBAT | power_in | Backup supply (1.8 to 3.6 V) for the RTC, external 32 kHz oscillator and backup registers when VDD is not present. |+| 2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13 or TAMPER-RTC, supplied through the power switch so output use is limited to 2 MHz mode with max 30 pF load and only one such pin as output at a time. |+| 3 | PC14-OSC32_IN | bidirectional | GPIO PC14 or 32 kHz oscillator input OSC32_IN, supplied through the power switch with output use limited to 2 MHz, 30 pF max, one pin at a time. |+| 4 | PC15-OSC32_OUT | bidirectional | GPIO PC15 or 32 kHz oscillator output OSC32_OUT, supplied through the power switch with output use limited to 2 MHz, 30 pF max, one pin at a time. |+| 5 | OSC_IN | input | Main 3-25 MHz oscillator input after reset; PD0 can be remapped onto this pin by software. |+| 6 | OSC_OUT | output | Main 3-25 MHz oscillator output after reset; PD1 can be remapped onto this pin by software. |+| 7 | NRST | bidirectional | Device reset input/output, main function NRST after reset. |+| 8 | PC0 | bidirectional | General-purpose I/O PC0 with alternate function ADC12_IN10. |+| 9 | PC1 | bidirectional | General-purpose I/O PC1 with alternate functions ADC12_IN11 and ETH_MII_MDC/ETH_RMII_MDC. |+| 10 | PC2 | bidirectional | General-purpose I/O PC2 with alternate functions ADC12_IN12 and ETH_MII_TXD2. |+| 11 | PC3 | bidirectional | General-purpose I/O PC3 with alternate functions ADC12_IN13 and ETH_MII_TX_CLK. |+| 12 | VSSA | power_in | Analog ground for ADC, reset blocks, RCs and PLL; must be connected to VSS. |+| 13 | VDDA | power_in | Analog supply 2.0 to 3.6 V (minimum 2.4 V when the ADC is used); must be connected to VDD. |+| 14 | PA0-WKUP | bidirectional | General-purpose I/O PA0 with WKUP, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR, TIM5_CH1 and ETH_MII_CRS_WKUP functions. |+| 15 | PA1 | bidirectional | General-purpose I/O PA1 with USART2_RTS, ADC12_IN1, TIM5_CH2, TIM2_CH2, ETH_MII_RX_CLK/ETH_RMII_REF_CLK functions. |+| 16 | PA2 | bidirectional | General-purpose I/O PA2 with USART2_TX, TIM5_CH3, ADC12_IN2, TIM2_CH3, ETH_MII_MDIO/ETH_RMII_MDIO functions. |+| 17 | PA3 | bidirectional | General-purpose I/O PA3 with USART2_RX, TIM5_CH4, ADC12_IN3, TIM2_CH4, ETH_MII_COL functions. |+| 18 | VSS_4 | power_in | Digital ground supply pin VSS_4. |+| 19 | VDD_4 | power_in | Digital supply pin VDD_4 for I/Os and internal regulator, 2.0 to 3.6 V. |+| 20 | PA4 | bidirectional | General-purpose I/O PA4 with SPI1_NSS, DAC_OUT1, USART2_CK, ADC12_IN4; remap SPI3_NSS/I2S3_WS. |+| 21 | PA5 | bidirectional | General-purpose I/O PA5 with SPI1_SCK, DAC_OUT2 and ADC12_IN5. |+| 22 | PA6 | bidirectional | General-purpose I/O PA6 with SPI1_MISO, ADC12_IN6, TIM3_CH1; remap TIM1_BKIN. |+| 23 | PA7 | bidirectional | General-purpose I/O PA7 with SPI1_MOSI, ADC12_IN7, TIM3_CH2, ETH_MII_RX_DV/ETH_RMII_CRS_DV; remap TIM1_CH1N. |+| 24 | PC4 | bidirectional | General-purpose I/O PC4 with ADC12_IN14 and ETH_MII_RXD0/ETH_RMII_RXD0. |+| 25 | PC5 | bidirectional | General-purpose I/O PC5 with ADC12_IN15 and ETH_MII_RXD1/ETH_RMII_RXD1. |+| 26 | PB0 | bidirectional | General-purpose I/O PB0 with ADC12_IN8, TIM3_CH3, ETH_MII_RXD2; remap TIM1_CH2N. |+| 27 | PB1 | bidirectional | General-purpose I/O PB1 with ADC12_IN9, TIM3_CH4, ETH_MII_RXD3; remap TIM1_CH3N. |+| 28 | PB2/BOOT1 | bidirectional | 5 V-tolerant I/O PB2 that also serves as the BOOT1 boot mode selection pin. |+| 29 | PB10 | bidirectional | 5 V-tolerant I/O PB10 with I2C2_SCL, USART3_TX, ETH_MII_RX_ER; remap TIM2_CH3. |+| 30 | PB11 | bidirectional | 5 V-tolerant I/O PB11 with I2C2_SDA, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX_EN; remap TIM2_CH4. |+| 31 | VSS_1 | power_in | Digital ground supply pin VSS_1. |+| 32 | VDD_1 | power_in | Digital supply pin VDD_1 for I/Os and internal regulator, 2.0 to 3.6 V. |+| 33 | PB12 | bidirectional | 5 V-tolerant I/O PB12 with SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX and ETH_MII_TXD0/ETH_RMII_TXD0. |+| 34 | PB13 | bidirectional | 5 V-tolerant I/O PB13 with SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and ETH_MII_TXD1/ETH_RMII_TXD1. |+| 35 | PB14 | bidirectional | 5 V-tolerant I/O PB14 with SPI2_MISO, TIM1_CH2N and USART3_RTS. |+| 36 | PB15 | bidirectional | 5 V-tolerant I/O PB15 with SPI2_MOSI/I2S2_SD and TIM1_CH3N. |+| 37 | PC6 | bidirectional | 5 V-tolerant I/O PC6 with I2S2_MCK; remap TIM3_CH1. |+| 38 | PC7 | bidirectional | 5 V-tolerant I/O PC7 with I2S3_MCK; remap TIM3_CH2. |+| 39 | PC8 | bidirectional | 5 V-tolerant I/O PC8; remap TIM3_CH3. |+| 40 | PC9 | bidirectional | 5 V-tolerant I/O PC9; remap TIM3_CH4. |+| 41 | PA8 | bidirectional | 5 V-tolerant I/O PA8 with USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO. |+| 42 | PA9 | bidirectional | 5 V-tolerant I/O PA9 with USART1_TX, TIM1_CH2 and OTG_FS_VBUS. |+| 43 | PA10 | bidirectional | 5 V-tolerant I/O PA10 with USART1_RX, TIM1_CH3 and OTG_FS_ID. |+| 44 | PA11 | bidirectional | 5 V-tolerant I/O PA11 with USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM. |+| 45 | PA12 | bidirectional | 5 V-tolerant I/O PA12 with USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR. |+| 46 | PA13 | bidirectional | 5 V-tolerant pin that is JTMS-SWDIO after reset; PA13 is its remap function. |+| 47 | VSS_2 | power_in | Digital ground supply pin VSS_2. |+| 48 | VDD_2 | power_in | Digital supply pin VDD_2 for I/Os and internal regulator, 2.0 to 3.6 V. |+| 49 | PA14 | bidirectional | 5 V-tolerant pin that is JTCK-SWCLK after reset; PA14 is its remap function. |+| 50 | PA15 | bidirectional | 5 V-tolerant pin that is JTDI after reset, with SPI3_NSS/I2S3_WS; remap TIM2_CH1_ETR, PA15, SPI1_NSS. |+| 51 | PC10 | bidirectional | 5 V-tolerant I/O PC10 with UART4_TX; remap USART3_TX, SPI3_SCK/I2S3_CK. |+| 52 | PC11 | bidirectional | 5 V-tolerant I/O PC11 with UART4_RX; remap USART3_RX, SPI3_MISO. |+| 53 | PC12 | bidirectional | 5 V-tolerant I/O PC12 with UART5_TX; remap USART3_CK, SPI3_MOSI/I2S3_SD. |+| 54 | PD2 | bidirectional | 5 V-tolerant I/O PD2 with TIM3_ETR and UART5_RX. |+| 55 | PB3 | bidirectional | 5 V-tolerant pin that is JTDO after reset, with SPI3_SCK/I2S3_CK; remap PB3, TRACESWO, TIM2_CH2, SPI1_SCK. |+| 56 | PB4 | bidirectional | 5 V-tolerant pin that is NJTRST after reset, with SPI3_MISO; remap PB4, TIM3_CH1, SPI1_MISO. |+| 57 | PB5 | bidirectional | I/O PB5 with I2C1_SMBA, SPI3_MOSI/I2S3_SD, ETH_MII_PPS_OUT; remap TIM3_CH2, SPI1_MOSI, CAN2_RX. |+| 58 | PB6 | bidirectional | 5 V-tolerant I/O PB6 with I2C1_SCL and TIM4_CH1; remap USART1_TX, CAN2_TX. |+| 59 | PB7 | bidirectional | 5 V-tolerant I/O PB7 with I2C1_SDA and TIM4_CH2; remap USART1_RX. |+| 60 | BOOT0 | input | Boot mode selection input. |+| 61 | PB8 | bidirectional | 5 V-tolerant I/O PB8 with TIM4_CH3 and ETH_MII_TXD3; remap I2C1_SCL, CAN1_RX. |+| 62 | PB9 | bidirectional | 5 V-tolerant I/O PB9 with TIM4_CH4; remap I2C1_SDA, CAN1_TX. |+| 63 | VSS_3 | power_in | Digital ground supply pin VSS_3. |+| 64 | VDD_3 | power_in | Digital supply pin VDD_3 for I/Os and internal regulator, 2.0 to 3.6 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-64(10x10) |+| Category | Embedded Processors & Controllers |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `STM32F105R8T6TR`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `stm32f105r8t6tr-etched.step` / `stm32f105r8t6tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32f105r8t6tr.step` / `stm32f105r8t6tr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588942310051106816) (108 pp, sha256 `ca4bad652e5eb36d`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm32f105r8t6tr-datasheet.pdf)
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Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "stm32f105r8t6tr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "stm32f105r8t6tr.kicad_sym",+ "stm32f105r8t6tr.kicad_mod",+ "stm32f105r8t6tr.glb",+ "stm32f105r8t6tr.step",+ "stm32f105r8t6tr.lbr",+ "docs/hero.png",+ "docs/stm32f105r8t6tr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "stm32f105r8t6tr-hero.glb",+ "stm32f105r8t6tr-hero.overlay.json"+ ],+ "component": {+ "mpn": "STM32F105R8T6TR",+ "manufacturer": "STMicroelectronics",+ "package": "LQFP-64(10x10)",+ "pin_count": 64,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588942310051106816",+ "parts": {+ "symbol": "stm32f105r8t6tr.kicad_sym",+ "footprint": "stm32f105r8t6tr.kicad_mod",+ "model_3d": "stm32f105r8t6tr-hero.glb",+ "model_3d_plain": "stm32f105r8t6tr.glb",+ "model_3d_step": "stm32f105r8t6tr-etched.step",+ "model_3d_step_plain": "stm32f105r8t6tr.step",+ "lbr": "stm32f105r8t6tr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2056061",+ "digikey": "497-18765-2-ND",+ "mouser": "511-STM32F105R8T6TR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T09:06:07Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-18765-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "511-STM32F105R8T6TR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VBAT",+ "type": "power_in",+ "description": "Backup supply (1.8 to 3.6 V) for the RTC, external 32 kHz oscillator and backup registers when VDD is not present."+ },+ {+ "number": "2",+ "name": "PC13-TAMPER-RTC",+ "type": "bidirectional",+ "description": "GPIO PC13 or TAMPER-RTC, supplied through the power switch so output use is limited to 2 MHz mode with max 30 pF load and only one such pin as output at a time."+ },+ {+ "number": "3",+ "name": "PC14-OSC32_IN",+ "type": "bidirectional",+ "description": "GPIO PC14 or 32 kHz oscillator input OSC32_IN, supplied through the power switch with output use limited to 2 MHz, 30 pF max, one pin at a time."+ },+ {+ "number": "4",+ "name": "PC15-OSC32_OUT",+ "type": "bidirectional",+ "description": "GPIO PC15 or 32 kHz oscillator output OSC32_OUT, supplied through the power switch with output use limited to 2 MHz, 30 pF max, one pin at a time."+ },+ {+ "number": "5",+ "name": "OSC_IN",+ "type": "input",+ "description": "Main 3-25 MHz oscillator input after reset; PD0 can be remapped onto this pin by software."+ },+ {+ "number": "6",+ "name": "OSC_OUT",+ "type": "output",+ "description": "Main 3-25 MHz oscillator output after reset; PD1 can be remapped onto this pin by software."+ },+ {+ "number": "7",+ "name": "NRST",+ "type": "bidirectional",+ "description": "Device reset input/output, main function NRST after reset."+ },+ {+ "number": "8",+ "name": "PC0",+ "type": "bidirectional",+ "description": "General-purpose I/O PC0 with alternate function ADC12_IN10."+ },+ {+ "number": "9",+ "name": "PC1",+ "type": "bidirectional",+ "description": "General-purpose I/O PC1 with alternate functions ADC12_IN11 and ETH_MII_MDC/ETH_RMII_MDC."+ },+ {+ "number": "10",+ "name": "PC2",+ "type": "bidirectional",+ "description": "General-purpose I/O PC2 with alternate functions ADC12_IN12 and ETH_MII_TXD2."+ },+ {+ "number": "11",+ "name": "PC3",+ "type": "bidirectional",+ "description": "General-purpose I/O PC3 with alternate functions ADC12_IN13 and ETH_MII_TX_CLK."+ },+ {+ "number": "12",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground for ADC, reset blocks, RCs and PLL; must be connected to VSS."+ },+ {+ "number": "13",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog supply 2.0 to 3.6 V (minimum 2.4 V when the ADC is used); must be connected to VDD."+ },+ {+ "number": "14",+ "name": "PA0-WKUP",+ "type": "bidirectional",+ "description": "General-purpose I/O PA0 with WKUP, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR, TIM5_CH1 and ETH_MII_CRS_WKUP functions."+ },+ {+ "number": "15",+ "name": "PA1",+ "type": "bidirectional",+ "description": "General-purpose I/O PA1 with USART2_RTS, ADC12_IN1, TIM5_CH2, TIM2_CH2, ETH_MII_RX_CLK/ETH_RMII_REF_CLK functions."+ },+ {+ "number": "16",+ "name": "PA2",+ "type": "bidirectional",+ "description": "General-purpose I/O PA2 with USART2_TX, TIM5_CH3, ADC12_IN2, TIM2_CH3, ETH_MII_MDIO/ETH_RMII_MDIO functions."+ },+ {+ "number": "17",+ "name": "PA3",+ "type": "bidirectional",+ "description": "General-purpose I/O PA3 with USART2_RX, TIM5_CH4, ADC12_IN3, TIM2_CH4, ETH_MII_COL functions."+ },+ {+ "number": "18",+ "name": "VSS_4",+ "type": "power_in",+ "description": "Digital ground supply pin VSS_4."+ },+ {+ "number": "19",+ "name": "VDD_4",+ "type": "power_in",+ "description": "Digital supply pin VDD_4 for I/Os and internal regulator, 2.0 to 3.6 V."+ },+ {+ "number": "20",+ "name": "PA4",+ "type": "bidirectional",+ "description": "General-purpose I/O PA4 with SPI1_NSS, DAC_OUT1, USART2_CK, ADC12_IN4; remap SPI3_NSS/I2S3_WS."+ },+ {+ "number": "21",+ "name": "PA5",+ "type": "bidirectional",+ "description": "General-purpose I/O PA5 with SPI1_SCK, DAC_OUT2 and ADC12_IN5."+ },+ {+ "number": "22",+ "name": "PA6",+ "type": "bidirectional",+ "description": "General-purpose I/O PA6 with SPI1_MISO, ADC12_IN6, TIM3_CH1; remap TIM1_BKIN."+ },+ {+ "number": "23",+ "name": "PA7",+ "type": "bidirectional",+ "description": "General-purpose I/O PA7 with SPI1_MOSI, ADC12_IN7, TIM3_CH2, ETH_MII_RX_DV/ETH_RMII_CRS_DV; remap TIM1_CH1N."+ },+ {+ "number": "24",+ "name": "PC4",+ "type": "bidirectional",+ "description": "General-purpose I/O PC4 with ADC12_IN14 and ETH_MII_RXD0/ETH_RMII_RXD0."+ },+ {+ "number": "25",+ "name": "PC5",+ "type": "bidirectional",+ "description": "General-purpose I/O PC5 with ADC12_IN15 and ETH_MII_RXD1/ETH_RMII_RXD1."+ },+ {+ "number": "26",+ "name": "PB0",+ "type": "bidirectional",+ "description": "General-purpose I/O PB0 with ADC12_IN8, TIM3_CH3, ETH_MII_RXD2; remap TIM1_CH2N."+ },+ {+ "number": "27",+ "name": "PB1",+ "type": "bidirectional",+ "description": "General-purpose I/O PB1 with ADC12_IN9, TIM3_CH4, ETH_MII_RXD3; remap TIM1_CH3N."+ },+ {+ "number": "28",+ "name": "PB2/BOOT1",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB2 that also serves as the BOOT1 boot mode selection pin."+ },+ {+ "number": "29",+ "name": "PB10",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB10 with I2C2_SCL, USART3_TX, ETH_MII_RX_ER; remap TIM2_CH3."+ },+ {+ "number": "30",+ "name": "PB11",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB11 with I2C2_SDA, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX_EN; remap TIM2_CH4."+ },+ {+ "number": "31",+ "name": "VSS_1",+ "type": "power_in",+ "description": "Digital ground supply pin VSS_1."+ },+ {+ "number": "32",+ "name": "VDD_1",+ "type": "power_in",+ "description": "Digital supply pin VDD_1 for I/Os and internal regulator, 2.0 to 3.6 V."+ },+ {+ "number": "33",+ "name": "PB12",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB12 with SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX and ETH_MII_TXD0/ETH_RMII_TXD0."+ },+ {+ "number": "34",+ "name": "PB13",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB13 with SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and ETH_MII_TXD1/ETH_RMII_TXD1."+ },+ {+ "number": "35",+ "name": "PB14",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB14 with SPI2_MISO, TIM1_CH2N and USART3_RTS."+ },+ {+ "number": "36",+ "name": "PB15",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB15 with SPI2_MOSI/I2S2_SD and TIM1_CH3N."+ },+ {+ "number": "37",+ "name": "PC6",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PC6 with I2S2_MCK; remap TIM3_CH1."+ },+ {+ "number": "38",+ "name": "PC7",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PC7 with I2S3_MCK; remap TIM3_CH2."+ },+ {+ "number": "39",+ "name": "PC8",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PC8; remap TIM3_CH3."+ },+ {+ "number": "40",+ "name": "PC9",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PC9; remap TIM3_CH4."+ },+ {+ "number": "41",+ "name": "PA8",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PA8 with USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO."+ },+ {+ "number": "42",+ "name": "PA9",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PA9 with USART1_TX, TIM1_CH2 and OTG_FS_VBUS."+ },+ {+ "number": "43",+ "name": "PA10",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PA10 with USART1_RX, TIM1_CH3 and OTG_FS_ID."+ },+ {+ "number": "44",+ "name": "PA11",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PA11 with USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM."+ },+ {+ "number": "45",+ "name": "PA12",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PA12 with USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR."+ },+ {+ "number": "46",+ "name": "PA13",+ "type": "bidirectional",+ "description": "5 V-tolerant pin that is JTMS-SWDIO after reset; PA13 is its remap function."+ },+ {+ "number": "47",+ "name": "VSS_2",+ "type": "power_in",+ "description": "Digital ground supply pin VSS_2."+ },+ {+ "number": "48",+ "name": "VDD_2",+ "type": "power_in",+ "description": "Digital supply pin VDD_2 for I/Os and internal regulator, 2.0 to 3.6 V."+ },+ {+ "number": "49",+ "name": "PA14",+ "type": "bidirectional",+ "description": "5 V-tolerant pin that is JTCK-SWCLK after reset; PA14 is its remap function."+ },+ {+ "number": "50",+ "name": "PA15",+ "type": "bidirectional",+ "description": "5 V-tolerant pin that is JTDI after reset, with SPI3_NSS/I2S3_WS; remap TIM2_CH1_ETR, PA15, SPI1_NSS."+ },+ {+ "number": "51",+ "name": "PC10",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PC10 with UART4_TX; remap USART3_TX, SPI3_SCK/I2S3_CK."+ },+ {+ "number": "52",+ "name": "PC11",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PC11 with UART4_RX; remap USART3_RX, SPI3_MISO."+ },+ {+ "number": "53",+ "name": "PC12",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PC12 with UART5_TX; remap USART3_CK, SPI3_MOSI/I2S3_SD."+ },+ {+ "number": "54",+ "name": "PD2",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PD2 with TIM3_ETR and UART5_RX."+ },+ {+ "number": "55",+ "name": "PB3",+ "type": "bidirectional",+ "description": "5 V-tolerant pin that is JTDO after reset, with SPI3_SCK/I2S3_CK; remap PB3, TRACESWO, TIM2_CH2, SPI1_SCK."+ },+ {+ "number": "56",+ "name": "PB4",+ "type": "bidirectional",+ "description": "5 V-tolerant pin that is NJTRST after reset, with SPI3_MISO; remap PB4, TIM3_CH1, SPI1_MISO."+ },+ {+ "number": "57",+ "name": "PB5",+ "type": "bidirectional",+ "description": "I/O PB5 with I2C1_SMBA, SPI3_MOSI/I2S3_SD, ETH_MII_PPS_OUT; remap TIM3_CH2, SPI1_MOSI, CAN2_RX."+ },+ {+ "number": "58",+ "name": "PB6",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB6 with I2C1_SCL and TIM4_CH1; remap USART1_TX, CAN2_TX."+ },+ {+ "number": "59",+ "name": "PB7",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB7 with I2C1_SDA and TIM4_CH2; remap USART1_RX."+ },+ {+ "number": "60",+ "name": "BOOT0",+ "type": "input",+ "description": "Boot mode selection input."+ },+ {+ "number": "61",+ "name": "PB8",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB8 with TIM4_CH3 and ETH_MII_TXD3; remap I2C1_SCL, CAN1_RX."+ },+ {+ "number": "62",+ "name": "PB9",+ "type": "bidirectional",+ "description": "5 V-tolerant I/O PB9 with TIM4_CH4; remap I2C1_SDA, CAN1_TX."+ },+ {+ "number": "63",+ "name": "VSS_3",+ "type": "power_in",+ "description": "Digital ground supply pin VSS_3."+ },+ {+ "number": "64",+ "name": "VDD_3",+ "type": "power_in",+ "description": "Digital supply pin VDD_3 for I/Os and internal regulator, 2.0 to 3.6 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 1 (PE2) shown with '-' in LQFP64 column of Table 5 but logically should be pin 1 of 64-pin packa; STM32F105R8T6TR is dual die variant; confirm pin assignments match exact device revision if strict h"+ ],+ "pages_sent": 50,+ "cost_usd": 0.6314,+ "at": "2026-10-07T09:05:38"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588942310051106816",+ "pages": 108,+ "sha256": "ca4bad652e5eb36d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "stm32f105r8t6tr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b0c827bc5c05552175d28affe44a5bd2ab45c9c36efff6ff07a74cc449b13db4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "stm32f105r8t6tr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "abdddb0d0aa24fdc9c0455119fca748c9aa8fe3acff43818da4ae5e6651a0579",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}