component
STM32F103RBT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSTM32F103RBT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F103RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for RTC, 32 kHz oscillator and backup registers; operating range 1.8-3.6 V; sourced through internal power switch when VDD is absent. |
| 2 | PC13 | bidirectional | GPIO; TAMPER-RTC alternate function; supplied through power switch, output limited to ≤2 MHz speed, ≤30 pF load, and ±3 mA maximum current. |
| 3 | PC14 | bidirectional | GPIO; OSC32_IN alternate function (32.768 kHz crystal oscillator input); supplied through power switch, output limited to ≤2 MHz speed, ≤30 pF load, and ±3 mA maximum current. |
| 4 | PC15 | bidirectional | GPIO; OSC32_OUT alternate function (32.768 kHz crystal oscillator output); supplied through power switch, output limited to ≤2 MHz speed, ≤30 pF load, and ±3 mA maximum current. |
| 5 | OSC_IN | input | 4-16 MHz high-speed external crystal oscillator input; PD0 GPIO function (CANRX remap) available only after software remap per Note 7 of Table 5. |
| 6 | OSC_OUT | output | High-speed crystal oscillator output; PD1 GPIO function (CANTX remap) available only after software remap per Note 7 of Table 5. |
| 7 | NRST | bidirectional | Active-low reset pin (I/O per Table 5) with permanent internal pull-up 30-50 kΩ; VIL ≤0.8 V, VIH ≥2 V; pulses <100 ns are filtered; minimum unfiltered reset pulse 300 ns. |
| 8 | PC0 | bidirectional | GPIO (not 5 V tolerant); alternate function ADC12_IN10 analog input, conversion range 0 to VREF+. |
| 9 | PC1 | bidirectional | GPIO (not 5 V tolerant); alternate function ADC12_IN11 analog input. |
| 10 | PC2 | bidirectional | GPIO (not 5 V tolerant); alternate function ADC12_IN12 analog input. |
| 11 | PC3 | bidirectional | GPIO (not 5 V tolerant); alternate function ADC12_IN13 analog input. |
| 12 | VSSA | power_in | Analog ground reference for ADC, reset block, RC oscillators and PLL; must be connected to VSS; VREF− is internally connected to VSSA in LQFP packages. |
| 13 | VDDA | power_in | Analog supply for ADC, reset, RC oscillators and PLL; 2.0-3.6 V (minimum 2.4 V when ADC is used); VREF+ is internally connected to VDDA in LQFP packages. |
| 14 | PA0-WKUP | bidirectional | GPIO (not 5 V tolerant); WKUP wakeup-from-Standby input; alternate functions ADC12_IN0/USART2_CTS/TIM2_CH1_ETR. |
| 15 | PA1 | bidirectional | GPIO (not 5 V tolerant); alternate functions ADC12_IN1/USART2_RTS/TIM2_CH2. |
| 16 | PA2 | bidirectional | GPIO (not 5 V tolerant); alternate functions ADC12_IN2/USART2_TX/TIM2_CH3. |
| 17 | PA3 | bidirectional | GPIO (not 5 V tolerant); alternate functions ADC12_IN3/USART2_RX/TIM2_CH4. |
| 18 | VSS_4 | power_in | Digital ground supply pin; decoupling capacitor (100 nF recommended) to adjacent VDD_4. |
| 19 | VDD_4 | power_in | Digital I/O and internal logic supply, 2.0-3.6 V. |
| 20 | PA4 | bidirectional | GPIO (not 5 V tolerant); alternate functions SPI1_NSS/USART2_CK/ADC12_IN4. |
| 21 | PA5 | bidirectional | GPIO (not 5 V tolerant); alternate functions SPI1_SCK/ADC12_IN5. |
| 22 | PA6 | bidirectional | GPIO (not 5 V tolerant); alternate functions SPI1_MISO/ADC12_IN6/TIM3_CH1; remap TIM1_BKIN. |
| 23 | PA7 | bidirectional | GPIO (not 5 V tolerant); alternate functions SPI1_MOSI/ADC12_IN7/TIM3_CH2; remap TIM1_CH1N. |
| 24 | PC4 | bidirectional | GPIO (not 5 V tolerant); alternate function ADC12_IN14 analog input. |
| 25 | PC5 | bidirectional | GPIO (not 5 V tolerant); alternate function ADC12_IN15 analog input. |
| 26 | PB0 | bidirectional | GPIO (not 5 V tolerant); alternate functions ADC12_IN8/TIM3_CH3; remap TIM1_CH2N. |
| 27 | PB1 | bidirectional | GPIO (not 5 V tolerant); alternate functions ADC12_IN9/TIM3_CH4; remap TIM1_CH3N. |
| 28 | PB2 | bidirectional | 5 V tolerant GPIO; also functions as BOOT1 boot-mode configuration input sampled at reset. |
| 29 | PB10 | bidirectional | 5 V tolerant GPIO; alternate functions I2C2_SCL/USART3_TX; remap TIM2_CH3. |
| 30 | PB11 | bidirectional | 5 V tolerant GPIO; alternate functions I2C2_SDA/USART3_RX; remap TIM2_CH4. |
| 31 | VSS_1 | power_in | Digital ground supply pin; decoupling capacitor (100 nF recommended) to adjacent VDD_1. |
| 32 | VDD_1 | power_in | Digital I/O and internal logic supply, 2.0-3.6 V. |
| 33 | PB12 | bidirectional | 5 V tolerant GPIO; alternate functions SPI2_NSS/I2C2_SMBAl/USART3_CK/TIM1_BKIN. |
| 34 | PB13 | bidirectional | 5 V tolerant GPIO; alternate functions SPI2_SCK/USART3_CTS/TIM1_CH1N. |
| 35 | PB14 | bidirectional | 5 V tolerant GPIO; alternate functions SPI2_MISO/USART3_RTS; remap TIM1_CH2N. |
| 36 | PB15 | bidirectional | 5 V tolerant GPIO; alternate function SPI2_MOSI; remap TIM1_CH3N. |
| 37 | PC6 | bidirectional | 5 V tolerant GPIO; alternate function TIM3_CH1. |
| 38 | PC7 | bidirectional | 5 V tolerant GPIO; alternate function TIM3_CH2. |
| 39 | PC8 | bidirectional | 5 V tolerant GPIO; alternate function TIM3_CH3. |
| 40 | PC9 | bidirectional | 5 V tolerant GPIO; alternate function TIM3_CH4. |
| 41 | PA8 | bidirectional | 5 V tolerant GPIO; alternate functions USART1_CK/TIM1_CH1/MCO (master clock output). |
| 42 | PA9 | bidirectional | 5 V tolerant GPIO; alternate functions USART1_TX/TIM1_CH2. |
| 43 | PA10 | bidirectional | 5 V tolerant GPIO; alternate functions USART1_RX/TIM1_CH3. |
| 44 | PA11 | bidirectional | 5 V tolerant GPIO; alternate functions USART1_CTS/CANRX/USBDM/TIM1_CH4. |
| 45 | PA12 | bidirectional | 5 V tolerant GPIO; alternate functions USART1_RTS/CANTX/USBDP; remap TIM1_ETR. |
| 46 | PA13 | bidirectional | 5 V tolerant GPIO; default function JTMS/SWDIO (JTAG/SWD debug); remappable to PA13 general-purpose I/O. |
| 47 | VSS_2 | power_in | Digital ground supply pin; decoupling capacitor (100 nF recommended) to adjacent VDD_2. |
| 48 | VDD_2 | power_in | Digital I/O and internal logic supply, 2.0-3.6 V. |
| 49 | PA14 | bidirectional | 5 V tolerant GPIO; default function JTCK/SWCLK (JTAG TCK / SWD clock); remappable to PA14 general-purpose I/O. |
| 50 | PA15 | bidirectional | 5 V tolerant GPIO; default function JTDI (JTAG data input); remap TIM2_CH1_ETR/PA15/SPI1_NSS. |
| 51 | PC10 | bidirectional | 5 V tolerant GPIO; alternate function USART3_TX. |
| 52 | PC11 | bidirectional | 5 V tolerant GPIO; alternate function USART3_RX. |
| 53 | PC12 | bidirectional | 5 V tolerant GPIO; alternate function USART3_CK. |
| 54 | PD2 | bidirectional | 5 V tolerant GPIO; alternate function TIM3_ETR (external trigger input). |
| 55 | PB3 | bidirectional | 5 V tolerant GPIO; default function JTDO/TRACESWO; remap TIM2_CH2/PB3/SPI1_SCK. |
| 56 | PB4 | bidirectional | 5 V tolerant GPIO; default function JNTRST (JTAG reset); remap TIM3_CH1/PB4/SPI1_MISO. |
| 57 | PB5 | bidirectional | GPIO (not 5 V tolerant); alternate function I2C1_SMBAl; remap TIM3_CH2/SPI1_MOSI. |
| 58 | PB6 | bidirectional | 5 V tolerant GPIO; alternate functions I2C1_SCL/TIM4_CH1; remap USART1_TX. |
| 59 | PB7 | bidirectional | 5 V tolerant GPIO; alternate functions I2C1_SDA/TIM4_CH2; remap USART1_RX. |
| 60 | BOOT0 | input | Boot mode selection pin sampled at reset; selects boot source (User Flash/System Memory/SRAM); input voltage range 0 to 5.5 V. |
| 61 | PB8 | bidirectional | 5 V tolerant GPIO; alternate function TIM4_CH3; remap I2C1_SCL/CANRX. |
| 62 | PB9 | bidirectional | 5 V tolerant GPIO; alternate function TIM4_CH4; remap I2C1_SDA/CANTX. |
| 63 | VSS_3 | power_in | Digital ground supply pin; decoupling capacitor (100 nF recommended) to adjacent VDD_3. |
| 64 | VDD_3 | power_in | Digital I/O and internal logic supply, 2.0-3.6 V; one 4.7 µF capacitor must be connected to this VDD pin per Figure 14 power supply scheme. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F103RBT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32f103rbt6-etched.step/stm32f103rbt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f103rbt6.step/stm32f103rbt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (105 pp, sha256
ceab0f159ae79118, retrieved 2026-09-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).