STM32F103C8T6 - Arm Cortex-M3 MCU (Blue Pill)

@@ -4,7 +4,7 @@   "slug": "stm32f103c8t6",   "title": "STM32F103C8T6 - Arm Cortex-M3 MCU (Blue Pill)",   "brief": "STMicroelectronics mainstream Arm Cortex-M3 MCU. 72 MHz, 64 KB Flash, 20 KB SRAM, USB, CAN, LQFP-48. The workhorse Blue Pill microcontroller.",-  "version": "0.2.6",+  "version": "0.2.7",   "tags": [     "component",     "microcontroller",@@ -160,8 +160,9 @@     "stm32f103c8t6-board.glb",     "thumbnails/**"   ],-  "changelog": "0.2.6: drop the pin-1 and datasheet voting sections (reporting a wrong field belongs in the sidebar, git-wiki #282); keep live price and stock.",+  "changelog": "0.2.7: pin-1 alignment applet, chip against footprint, compact line plus modal.",   "applet_connect": [+    "https://verify-3i7rt4do98l3.adom.cloud",     "https://component-ocean-jk89eeqplwfl.adom.cloud"   ],   "sections": [

@@ -135,6 +135,13 @@ tr[data-pin].hl td,tr[data-pin].hl td.data{color:var(--text)}   <div class=pintbl><div class=pingroup><h3>POWER <span style="color:var(--text-3);font-weight:400">(9)</span></h3><table><thead><tr><th style=width:44px>Pin</th><th style=width:170px>Name</th><th style=width:70px>Type</th><th>Function (datasheet)</th></tr></thead><tbody><tr data-pin="1"><td class=data>1</td><td class=data>VBAT</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Backup battery supply for RTC and backup registers. Typical operating range 1.8 to 3.6 V. Supplies the RTC and backup domain when VDD is off.</td></tr><tr data-pin="8"><td class=data>8</td><td class=data>VSSA</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Analog ground reference for ADC, reset block, PLL, and analog peripherals. Connect to digital ground at a single point.</td></tr><tr data-pin="9"><td class=data>9</td><td class=data>VDDA</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Analog supply for ADC, reset block, PLL, and analog I/O. 2.0 to 3.6 V. Decouple with 1 µF + 10 nF close to the pin.</td></tr><tr data-pin="23"><td class=data>23</td><td class=data>VSS_1</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Digital ground, group 1. Connect to the ground plane; keep short return path to VDD_1 decoupling.</td></tr><tr data-pin="24"><td class=data>24</td><td class=data>VDD_1</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Digital supply, group 1. 2.0 to 3.6 V. Decouple with 100 nF close to the pin.</td></tr><tr data-pin="35"><td class=data>35</td><td class=data>VSS_2</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Digital ground, group 2. Connect to the ground plane; pair with VDD_2 decoupling.</td></tr><tr data-pin="36"><td class=data>36</td><td class=data>VDD_2</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Digital supply, group 2. 2.0 to 3.6 V. Decouple with 100 nF close to the pin.</td></tr><tr data-pin="47"><td class=data>47</td><td class=data>VSS_3</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Digital ground, group 3. Connect to the ground plane; pair with VDD_3 decoupling.</td></tr><tr data-pin="48"><td class=data>48</td><td class=data>VDD_3</td><td><span class="tbadge t-power">Power</span></td><td class=note style="color:var(--text-2)">Digital supply, group 3. 2.0 to 3.6 V. Decouple with 100 nF close to the pin.</td></tr></tbody></table></div><div class=pingroup><h3>GPIO <span style="color:var(--text-3);font-weight:400">(26)</span></h3><table><thead><tr><th style=width:44px>Pin</th><th style=width:170px>Name</th><th style=width:70px>Type</th><th>Function (datasheet)</th></tr></thead><tbody><tr data-pin="2"><td class=data>2</td><td class=data>PC13-TAMPER-RTC</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port C bit 13, muxed with TAMPER input and RTC output. Supplied through the backup power switch (limited to 3 mA sink); output speed limited to 2 MHz with max 30 pF load; must not source current.</td></tr><tr data-pin="10"><td class=data>10</td><td class=data>PA0-WKUP</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 0, 5 V-tolerant when configured as digital input. Alternate functions: standby WKUP, USART2_CTS (remap), ADC12_IN0, TIM2_CH1_ETR.</td></tr><tr data-pin="11"><td class=data>11</td><td class=data>PA1</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 1. Alternate functions: USART2_RTS, ADC12_IN1, TIM2_CH2.</td></tr><tr data-pin="12"><td class=data>12</td><td class=data>PA2</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 2. Alternate functions: USART2_TX, ADC12_IN2, TIM2_CH3.</td></tr><tr data-pin="13"><td class=data>13</td><td class=data>PA3</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 3. Alternate functions: USART2_RX, ADC12_IN3, TIM2_CH4.</td></tr><tr data-pin="14"><td class=data>14</td><td class=data>PA4</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 4. Alternate functions: SPI1_NSS, USART2_CK, ADC12_IN4.</td></tr><tr data-pin="15"><td class=data>15</td><td class=data>PA5</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 5. Alternate functions: SPI1_SCK, ADC12_IN5.</td></tr><tr data-pin="16"><td class=data>16</td><td class=data>PA6</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 6. Alternate functions: SPI1_MISO, ADC12_IN6, TIM3_CH1; remap: TIM1_BKIN.</td></tr><tr data-pin="17"><td class=data>17</td><td class=data>PA7</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 7. Alternate functions: SPI1_MOSI, ADC12_IN7, TIM3_CH2; remap: TIM1_CH1N.</td></tr><tr data-pin="18"><td class=data>18</td><td class=data>PB0</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 0. Alternate functions: ADC12_IN8, TIM3_CH3; remap: TIM1_CH2N.</td></tr><tr data-pin="19"><td class=data>19</td><td class=data>PB1</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 1. Alternate functions: ADC12_IN9, TIM3_CH4; remap: TIM1_CH3N.</td></tr><tr data-pin="20"><td class=data>20</td><td class=data>PB2</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 2, 5 V-tolerant. Doubles as BOOT1 boot mode selection input sampled at reset.</td></tr><tr data-pin="21"><td class=data>21</td><td class=data>PB10</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 10, 5 V-tolerant. Alternate functions: I2C2_SCL, USART3_TX; remap: TIM2_CH3.</td></tr><tr data-pin="22"><td class=data>22</td><td class=data>PB11</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 11, 5 V-tolerant. Alternate functions: I2C2_SDA, USART3_RX; remap: TIM2_CH4.</td></tr><tr data-pin="25"><td class=data>25</td><td class=data>PB12</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 12, 5 V-tolerant. Alternate functions: SPI2_NSS, I2C2_SMBAl, USART3_CK, TIM1_BKIN.</td></tr><tr data-pin="26"><td class=data>26</td><td class=data>PB13</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 13, 5 V-tolerant. Alternate functions: SPI2_SCK, USART3_CTS, TIM1_CH1N.</td></tr><tr data-pin="27"><td class=data>27</td><td class=data>PB14</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 14, 5 V-tolerant. Alternate functions: SPI2_MISO, USART3_RTS, TIM1_CH2N.</td></tr><tr data-pin="28"><td class=data>28</td><td class=data>PB15</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 15, 5 V-tolerant. Alternate functions: SPI2_MOSI, TIM1_CH3N.</td></tr><tr data-pin="29"><td class=data>29</td><td class=data>PA8</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 8, 5 V-tolerant. Alternate functions: USART1_CK, TIM1_CH1, MCO (master clock output).</td></tr><tr data-pin="30"><td class=data>30</td><td class=data>PA9</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 9, 5 V-tolerant. Alternate functions: USART1_TX, TIM1_CH2.</td></tr><tr data-pin="31"><td class=data>31</td><td class=data>PA10</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 10, 5 V-tolerant. Alternate functions: USART1_RX, TIM1_CH3.</td></tr><tr data-pin="41"><td class=data>41</td><td class=data>PB5</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 5 (NOT 5 V-tolerant on this pin). Alternate functions: I2C1_SMBAl; remap: TIM3_CH2, SPI1_MOSI.</td></tr><tr data-pin="42"><td class=data>42</td><td class=data>PB6</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 6, 5 V-tolerant. Alternate functions: I2C1_SCL, TIM4_CH1; remap: USART1_TX.</td></tr><tr data-pin="43"><td class=data>43</td><td class=data>PB7</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 7, 5 V-tolerant. Alternate functions: I2C1_SDA, TIM4_CH2; remap: USART1_RX.</td></tr><tr data-pin="45"><td class=data>45</td><td class=data>PB8</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 8, 5 V-tolerant. Alternate functions: TIM4_CH3; remap: I2C1_SCL, CANRX.</td></tr><tr data-pin="46"><td class=data>46</td><td class=data>PB9</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 9, 5 V-tolerant. Alternate functions: TIM4_CH4; remap: I2C1_SDA, CANTX.</td></tr></tbody></table></div><div class=pingroup><h3>TIMING <span style="color:var(--text-3);font-weight:400">(4)</span></h3><table><thead><tr><th style=width:44px>Pin</th><th style=width:170px>Name</th><th style=width:70px>Type</th><th>Function (datasheet)</th></tr></thead><tbody><tr data-pin="3"><td class=data>3</td><td class=data>PC14-OSC32_IN</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port C bit 14, muxed with 32 kHz LSE oscillator input (OSC32_IN). Backup-domain pin routed through the power switch; same 2 MHz / 30 pF drive limitation as PC13.</td></tr><tr data-pin="4"><td class=data>4</td><td class=data>PC15-OSC32_OUT</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port C bit 15, muxed with 32 kHz LSE oscillator output (OSC32_OUT). Backup-domain pin routed through the power switch; same 2 MHz / 30 pF drive limitation as PC13/PC14.</td></tr><tr data-pin="5"><td class=data>5</td><td class=data>PD0-OSC_IN</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">HSE crystal oscillator input (OSC_IN) after reset; remappable to GPIO PD0 by software. In GPIO mode limited to 50 MHz output. Connect to 4-16 MHz crystal or external clock.</td></tr><tr data-pin="6"><td class=data>6</td><td class=data>PD1-OSC_OUT</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">HSE crystal oscillator output (OSC_OUT) after reset; remappable to GPIO PD1 by software. In GPIO mode limited to 50 MHz output.</td></tr></tbody></table></div><div class=pingroup><h3>CONTROL <span style="color:var(--text-3);font-weight:400">(2)</span></h3><table><thead><tr><th style=width:44px>Pin</th><th style=width:170px>Name</th><th style=width:70px>Type</th><th>Function (datasheet)</th></tr></thead><tbody><tr data-pin="7"><td class=data>7</td><td class=data>NRST</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">Active-low bidirectional device reset. Pulled low by internal or external reset sources; external pull-up recommended (typ 40 kΩ internal weak pull-up).</td></tr><tr data-pin="44"><td class=data>44</td><td class=data>BOOT0</td><td></td><td class=note style="color:var(--text-2)">Boot mode selection input sampled at reset (with BOOT1/PB2): selects boot from Flash, System memory (bootloader), or embedded SRAM. Must be tied to a defined logic level.</td></tr></tbody></table></div><div class=pingroup><h3>USB <span style="color:var(--text-3);font-weight:400">(2)</span></h3><table><thead><tr><th style=width:44px>Pin</th><th style=width:170px>Name</th><th style=width:70px>Type</th><th>Function (datasheet)</th></tr></thead><tbody><tr data-pin="32"><td class=data>32</td><td class=data>PA11</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 11, 5 V-tolerant. Alternate functions: USART1_CTS, CANRX, USBDM (USB D-), TIM1_CH4.</td></tr><tr data-pin="33"><td class=data>33</td><td class=data>PA12</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 12, 5 V-tolerant. Alternate functions: USART1_RTS, CANTX, USBDP (USB D+), TIM1_ETR.</td></tr></tbody></table></div><div class=pingroup><h3>DEBUG <span style="color:var(--text-3);font-weight:400">(5)</span></h3><table><thead><tr><th style=width:44px>Pin</th><th style=width:170px>Name</th><th style=width:70px>Type</th><th>Function (datasheet)</th></tr></thead><tbody><tr data-pin="34"><td class=data>34</td><td class=data>PA13</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 13, 5 V-tolerant. Default after reset: JTMS/SWDIO (serial-wire debug data/JTAG mode select). Can be released to GPIO via SWJ-DP disable.</td></tr><tr data-pin="37"><td class=data>37</td><td class=data>PA14</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 14, 5 V-tolerant. Default after reset: JTCK/SWCLK (serial-wire debug clock/JTAG clock).</td></tr><tr data-pin="38"><td class=data>38</td><td class=data>PA15</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port A bit 15, 5 V-tolerant. Default after reset: JTDI (JTAG data in). Remappable to TIM2_CH1_ETR/PA15/SPI1_NSS.</td></tr><tr data-pin="39"><td class=data>39</td><td class=data>PB3</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 3, 5 V-tolerant. Default after reset: JTDO / TRACESWO. Remappable to TIM2_CH2, PB3, SPI1_SCK.</td></tr><tr data-pin="40"><td class=data>40</td><td class=data>PB4</td><td><span class="tbadge t-io">I/O</span></td><td class=note style="color:var(--text-2)">GPIO port B bit 4, 5 V-tolerant. Default after reset: NJTRST (JTAG reset, active low). Remappable to TIM3_CH1, PB4, SPI1_MISO.</td></tr></tbody></table></div></div> </div> +<h2 id=pin1>Pin 1, chip against footprint <span class=s>the datasheet already says which pad is pin 1; what matters is whether pin 1 on the chip lands on pin 1 of the footprint, because when they disagree the part goes down rotated</span></h2>+<script src="https://verify-3i7rt4do98l3.adom.cloud/applet.js"></script>+<adom-verify+  page="STM32F103C8T6" fact="pin-1-registration"+  chip-image="https://wiki.adom.inc/blob/component/stm32f103c8t6/pin1/chip-top.png"+  footprint-svg="https://wiki.adom.inc/blob/component/stm32f103c8t6/pin1/footprint.svg"></adom-verify>+ <h2 id=sourcing>Price and stock <span class=s>the one thing on this page that cannot be baked: it changes without the page changing, so the button asks Component Ocean live</span></h2> <script src="https://component-ocean-jk89eeqplwfl.adom.cloud/applet.js"></script> <adom-sourcing mpn="STM32F103C8T6"></adom-sourcing>