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Name	Last commit message	Last updated
docs	stm32f042k6u6tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
viewers	stm32f042k6u6tr: viewers · Ray	4d ago
package.json	Publish 0.1.0 · Ray	4d ago
page.json	Set visibility: public · Ray	4d ago
README.md	Initial commit: component/stm32f042k6u6tr · Ray	4d ago
stm32f042k6u6tr-etched.fit.json	stm32f042k6u6tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
stm32f042k6u6tr-etched.glb	stm32f042k6u6tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
stm32f042k6u6tr-etched.step	stm32f042k6u6tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
stm32f042k6u6tr.glb	Publish 0.1.0 · Ray	4d ago
stm32f042k6u6tr.kicad_mod	Publish 0.1.0 · Ray	4d ago
stm32f042k6u6tr.kicad_sym	Publish 0.1.0 · Ray	4d ago
stm32f042k6u6tr.lbr	Publish 0.1.0 · Ray	4d ago
stm32f042k6u6tr.step	Publish 0.1.0 · Ray	4d ago

STM32F042K6U6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-32(5x5)

STM32F042K6U6TR from STMicroelectronics, in a UFQFPN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Digital power supply, 2.0 to 3.6 V
2	PF0-OSC_IN	bidirectional	GPIO or external oscillator input for 4-32 MHz crystal with CRS_SYNC and I2C1_SDA alternate functions
3	PF1-OSC_OUT	bidirectional	GPIO or external oscillator output for crystal with I2C1_SCL alternate function
4	NRST	bidirectional	Device reset input / internal reset output (active low) with embedded weak pull-up resistor
5	VDDA	power_in	Analog power supply, from VDD to 3.6 V (2.4 V minimum if ADC is used), must be >= VDD
6	PA0	bidirectional	TTa I/O with USART2_CTS, TIM2_CH1_ETR, TSC_G1_IO1, RTC_TAMP2, WKUP1, ADC_IN0 alternate functions
7	PA1	bidirectional	TTa I/O with USART2_RTS, TIM2_CH2, TSC_G1_IO2, EVENTOUT, ADC_IN1 alternate functions
8	PA2	bidirectional	TTa I/O with USART2_TX, TIM2_CH3, TSC_G1_IO3, ADC_IN2, WKUP4 alternate functions
9	PA3	bidirectional	TTa I/O with USART2_RX, TIM2_CH4, TSC_G1_IO4, ADC_IN3 alternate functions
10	PA4	bidirectional	TTa I/O with SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK, USB_NOE, ADC_IN4 alternate functions
11	PA5	bidirectional	TTa I/O with SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2, ADC_IN5 alternate functions
12	PA6	bidirectional	TTa I/O with SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, TSC_G2_IO3, EVENTOUT, ADC_IN6 alternate functions
13	PA7	bidirectional	TTa I/O with SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, TSC_G2_IO4, EVENTOUT, ADC_IN7 alternate functions
14	PB0	bidirectional	TTa I/O with TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, ADC_IN8 alternate functions
15	PB1	bidirectional	TTa I/O with TIM3_CH4, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3, ADC_IN9 alternate functions
16	PB2	bidirectional	FT 5V-tolerant I/O with TSC_G3_IO4 alternate function for capacitive sensing
17	VDDIO2	power_in	I/O power supply for high-performance I/Os, 1.65 to 3.6 V, independent from VDD but VDD must be present first
18	PA8	bidirectional	FT I/O supplied by VDDIO2 with USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC alternate functions
19	PA9	bidirectional	FTf I/O supplied by VDDIO2 with USART1_TX, TIM1_CH2, TSC_G4_IO1, I2C1_SCL alternate functions
20	PA10	bidirectional	FTf I/O supplied by VDDIO2 with USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2, I2C1_SDA alternate functions
21	PA11	bidirectional	FTf I/O supplied by VDDIO2 with CAN_RX, USART1_CTS, TIM1_CH4, TSC_G4_IO3, EVENTOUT, I2C1_SCL, USB_DM alternate functions; can be remapped to PA9 position using SYSCFG_CFGR1
22	PA12	bidirectional	FTf I/O supplied by VDDIO2 with CAN_TX, USART1_RTS, TIM1_ETR, TSC_G4_IO4, EVENTOUT, I2C1_SDA, USB_DP alternate functions; can be remapped to PA10 position using SYSCFG_CFGR1
23	PA13	bidirectional	FT I/O supplied by VDDIO2 configured as SWDIO at reset with IR_OUT, USB_NOE alternate functions
24	PA14	bidirectional	FT I/O supplied by VDDIO2 configured as SWCLK at reset with USART2_TX alternate function
25	PA15	bidirectional	FT I/O supplied by VDDIO2 with SPI1_NSS, I2S1_WS, USART2_RX, TIM2_CH1_ETR, EVENTOUT, USB_NOE alternate functions
26	PB3	bidirectional	FT I/O with SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT alternate functions
27	PB4	bidirectional	FT I/O with SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT alternate functions
28	PB5	bidirectional	FT I/O with SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2, WKUP6 alternate functions
29	PB6	bidirectional	FTf I/O with I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3 alternate functions
30	PB7	bidirectional	FTf I/O with I2C1_SDA, USART1_RX, TIM17_CH1N, TSC_G5_IO4 alternate functions
0	VSS/VSSA (Exposed Pad)	power_in	Ground for analog and digital domains, exposed die pad on underside of package must be soldered to PCB ground

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	UFQFPN-32(5x5)
Category	Embedded Processors & Controllers
Pins	32

CAD (KiCad official)

Symbol: STM32F042K6U6TR
Footprint: Package_DFN_QFN:UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
3D model: UFQFPN-32(5x5) (KiCad packages3D, STEP)
3D model files: stm32f042k6u6tr-etched.step / stm32f042k6u6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f042k6u6tr.step / stm32f042k6u6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (117 pp, sha256 7af7ec8f5a596b23, retrieved 2026-10-01, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF