STGAP2SICSNTR

{
  "schema_version": 1,
  "type": "component",
  "slug": "stgap2sicsntr",
  "title": "STGAP2SICSNTR",
  "brief": "STMicroelectronics Isolators - Gate Drivers, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "power management (pmic)",
    "stgap2sicsntr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "STGAP2SICSNTR",
    "manufacturer": "STMicroelectronics",
    "package": "SO-8",
    "pin_count": 8,
    "category": "Power Management (PMIC)",
    "subcategory": "Isolators - Gate Drivers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603078722488578048",
    "parts": {
      "symbol": "stgap2sicsntr.kicad_sym",
      "footprint": "stgap2sicsntr.kicad_mod",
      "model_3d": "stgap2sicsntr-hero.glb",
      "model_3d_plain": "stgap2sicsntr.glb",
      "model_3d_step": "stgap2sicsntr-etched.step",
      "model_3d_step_plain": "stgap2sicsntr.step",
      "lbr": "stgap2sicsntr.lbr"
    },
    "distributor_links": {
      "lcsc": "C5267665",
      "digikey": "497-STGAP2SICSNTR-ND",
      "mouser": "511-STGAP2SICSNTR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T21:21:07Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "497-STGAP2SICSNTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "511-STGAP2SICSNTR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Driver logic supply voltage, recommended 3.1 V to 5.5 V vs. GND (absolute maximum 6.5 V), with a 100 nF plus 1 µF to 10 µF bypass placed close to the pin."
      },
      {
        "number": "2",
        "name": "IN+",
        "type": "input",
        "description": "Driver logic input, active high, with hysteresis thresholds of 0.33·VDD (typ) low and 0.66·VDD (typ) high, 100 kΩ pull-down, and a 20 to 40 ns deglitch filter."
      },
      {
        "number": "3",
        "name": "IN-",
        "type": "input",
        "description": "Driver logic input, active low, with the same threshold, pull-down and deglitch characteristics as IN+; logic pins are rated 0 to 5.5 V vs. GND."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Driver logic ground, the reference for VDD and the logic inputs IN+ and IN-."
      },
      {
        "number": "5",
        "name": "VH",
        "type": "power_in",
        "description": "Gate driving positive supply referenced to GNDISO, with recommended maximum 26 V, absolute maximum 28 V, and UVLO turn-on threshold of 14.6 to 16.4 V."
      },
      {
        "number": "6",
        "name": "GON",
        "type": "output",
        "description": "Source output (separated-output option, GON-GOFF part) that delivers up to 4 A source current at 25 °C and drives high to VH-0.125 V (typ) at 100 mA."
      },
      {
        "number": "7",
        "name": "GOFF",
        "type": "output",
        "description": "Sink output (separated-output option, GON-GOFF part) that sinks up to 4 A at 25 °C and drives low to 120 mV (typ) at 100 mA, with a SafeClp active clamp of 2.3 V (typ)."
      },
      {
        "number": "8",
        "name": "GNDISO",
        "type": "power_in",
        "description": "Isolated ground for the gate driving section, the reference for VH and the GON/GOFF outputs."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: STGAP2SiCSNTR is the GON-GOFF (separated outputs) order code per Table 10. Pins 6 and 7 are labelled; The Figure 3 pin-callout text in the extracted datasheet is garbled. Pin numbers for GND (4) and VH ; Pin types use KiCad classes: VDD, VH, GNDISO and GND are classed as power_in per the instruction tha"
        ],
        "pages_sent": 24,
        "cost_usd": 0.0728,
        "at": "2026-10-08T21:20:29"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603078722488578048",
        "pages": 24,
        "sha256": "3cdd11d41062afa9",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "stgap2sicsntr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "stgap2sicsntr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "132c695ca2d6c4b70e1cecd9f992a205e729c6f49ae258f9f057e413bcf0f675",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "STMicroelectronics",
      "Package": "SO-8",
      "Category": "Power Management (PMIC)",
      "Pins": "8"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "stgap2sicsntr"
  ],
  "discovery_pitch": "STGAP2SICSNTR (STMicroelectronics) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "stgap2sicsntr.kicad_sym",
    "stgap2sicsntr.kicad_mod",
    "stgap2sicsntr.glb",
    "stgap2sicsntr.step",
    "stgap2sicsntr.lbr",
    "docs/hero.png",
    "docs/stgap2sicsntr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "stgap2sicsntr-hero.glb",
    "stgap2sicsntr-hero.overlay.json"
  ],
  "visibility": {
    "public": true
  }
}