STF40N60M2 from STMicroelectronics, in a TO-220-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	G	input	Gate terminal; gate-source voltage is limited to ±25 V (VGS).
2	D	passive	Drain terminal; drain-source voltage is rated 600 V and continuous drain current 34 A at TC = 25 °C.
3	S	passive	Source terminal; source-drain diode forward current is rated 34 A continuous (ISD).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	TO-220-3
Category	Transistors/Thyristors
Pins	3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Drain-source voltage	VDS			600	V		2
Gate-source voltage	VGS	-25		25	V		2
Drain current (continuous)	ID			34	A	TC = 25 °C	2
Drain current (continuous)	ID			22	A	TC = 100 °C	2
Drain current (pulsed)	IDM			136	A		2
Total power dissipation TO-220FP	PTOT			40	W	TC = 25 °C	2
Peak diode recovery voltage slope	dv/dt			15	V/ns		2
MOSFET dv/dt ruggedness	dv/dt			50	V/ns	VDD = 480 V	2
Insulation withstand voltage (RMS) TO-220FP	VISO			2.5	kV	t = 1 s; TC = 25 °C	2
Storage temperature range	Tstg	-55		150	°C		2
Avalanche current, repetitive or not-repetitive	IAR			6	A	pulse width limited by TJ max.	2
Single pulse avalanche energy	EAS			500	mJ	starting TJ = 25 °C, ID = IAR, VDD = 50 V	2
Thermal resistance, junction-to-case TO-220FP	RthJC			3.13	°C/W		2
Thermal resistance, junction-to-ambient TO-220FP	RthJA			62.5	°C/W		2
Drain-source breakdown voltage	V(BR)DSS	600			V	ID = 1 mA, VGS = 0 V	3
Zero gate voltage drain current	IDSS			1	µA	VGS = 0 V, VDS = 600 V	3
Zero gate voltage drain current at TC = 125 °C	IDSS			100	µA	VGS = 0 V, VDS = 600 V, TC = 125 °C	3
Gate body leakage current	IGSS	-10		10	µA	VDS = 0 V, VGS = ±25 V	3
Gate threshold voltage	VGS(th)	2	3	4	V	VDS = VGS, ID = 250 µA	3
Static drain-source on-resistance	RDS(on)		78	88	Ω	VGS = 10 V, ID = 17 A	3
Forward on voltage	VSD			1.6	V	ISD = 34 A, VGS = 0 V	4
Input capacitance	Ciss		2500		pF	VDS = 100 V, f = 1 MHz, VGS = 0 V	3
Output capacitance	Coss		117		pF	VDS = 100 V, f = 1 MHz, VGS = 0 V	3
Reverse transfer capacitance	Crss		2.4		pF	VDS = 100 V, f = 1 MHz, VGS = 0 V	3
Equivalent capacitance time related	Coss eq.		342		pF	VDS = 0 to 480 V, VGS = 0 V	3
Total gate charge	Qg		57		nC	VDD = 480 V, ID = 4.5 A, VGS = 0 to 10 V	3
Gate-source charge	Qgs		10		nC	VDD = 480 V, ID = 4.5 A, VGS = 0 to 10 V	3
Gate-drain charge	Qgd		25.5		nC	VDD = 480 V, ID = 4.5 A, VGS = 0 to 10 V	3
Intrinsic gate resistance	Rg		4.4		Ω	f = 1 MHz, ID = 0 A	3
Turn-on delay time	td(on)		20.5		ns	VDD = 300 V, ID = 34 A, RG = 4.7 Ω, VGS = 10 V	3
Rise time	tr		13.5		ns	VDD = 300 V, ID = 34 A, RG = 4.7 Ω, VGS = 10 V	3
Turn-off delay time	td(off)		96		ns	VDD = 300 V, ID = 34 A, RG = 4.7 Ω, VGS = 10 V	3
Fall time	tf		11		ns	VDD = 300 V, ID = 34 A, RG = 4.7 Ω, VGS = 10 V	3
Source-drain current	ISD		34		A		4
Source-drain current (pulsed)	ISDM		136		A		4
Reverse recovery time	trr		440		ns	ISD = 34 A, di/dt = 100 A/µs, VDD = 60 V	4
Reverse recovery charge	Qrr		8.2		µC	ISD = 34 A, di/dt = 100 A/µs, VDD = 60 V	4
Reverse recovery current	IRRM		37		A	ISD = 34 A, di/dt = 100 A/µs, VDD = 60 V	4
Reverse recovery time at TJ = 150 °C	trr		568		ns	ISD = 34 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C	4
Reverse recovery charge at TJ = 150 °C	Qrr		11.5		µC	ISD = 34 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C	4
Reverse recovery current at TJ = 150 °C	IRRM		40.5		A	ISD = 34 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C	4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	Abs		Updated title in cover page. Updated Table 2: Absolute maximum ratings, Table 5: On /off states, Table 6: Dynamic and	13

CAD (KiCad official)

Symbol: STF40N60M2
Footprint: Package_TO_SOT_THT:TO-220-3_Vertical
3D model: TO-220-3 (KiCad packages3D, STEP)
3D model files: stf40n60m2-etched.step / stf40n60m2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stf40n60m2.step / stf40n60m2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (15 pp, sha256 f8eb5d4cef832010, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STF40N60M2

Verified STF40N60M2

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3D Model

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