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docs std45nf75t4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain ST… · Ray 23d ago
viewers std45nf75t4: viewers · Ray 2mo ago
package.json Publish 0.1.0 · Ray 2mo ago
page.json std45nf75t4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain ST… · Ray 23d ago
README.md std45nf75t4: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago
std45nf75t4-etched.fit.json std45nf75t4: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
std45nf75t4-etched.glb std45nf75t4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain ST… · Ray 23d ago
std45nf75t4-etched.step std45nf75t4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain ST… · Ray 23d ago
std45nf75t4.glb Publish 0.1.0 · Ray 2mo ago
std45nf75t4.kicad_mod Publish 0.1.0 · Ray 2mo ago
std45nf75t4.kicad_sym Publish 0.1.0 · Ray 2mo ago
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std45nf75t4.step Publish 0.1.0 · Ray 2mo ago

STD45NF75T4

STMicroelectronics · MOSFETs · DPAK

STD45NF75T4 from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate. Insulated gate control terminal. Absolute maximum VGS = ±20 V. Typical gate threshold voltage VGS(th) = 2 to 4 V (at ID = 250 µA). Total gate charge Qg ≈ 60 nC typ (80 nC max) at VGS = 0 to 10 V, VDD = 60 V, ID = 40 A.
2 D passive Drain. Also electrically connected to the exposed TAB (thermal pad) of the DPAK package. VDS max = 75 V; continuous ID = 40 A at TC = 25 °C (30 A at TC = 100 °C); pulsed IDM = 160 A. Static RDS(on) = 18 mΩ typ / 24 mΩ max at VGS = 10 V, ID = 20 A.
3 S passive Source. Reference terminal for the MOSFET and anode of the intrinsic body diode. Body-diode forward voltage VSD ≈ 1.5 V max at ISD = 40 A, VGS = 0 V; trr ≈ 120 ns typ, Qrr ≈ 410 nC typ.
TAB D passive Exposed metal tab on the back of the DPAK package, internally connected to the drain (pin 2). Used as the primary thermal path to the PCB copper pour; Rthj-case = 1.2 °C/W, Rthj-pcb = 50 °C/W on a 1 in² 2 oz FR-4 board.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DPAK
Category Transistors/Thyristors
Pins 4

Ordering variants

Same part, different packaging or reel option.

  • STD45NF75T4

CAD (KiCad official)

  • Symbol: STD45NF75T4
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: DPAK (KiCad packages3D, STEP)
  • 3D model files: std45nf75t4-etched.step / std45nf75t4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); std45nf75t4.step / std45nf75t4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 69571e1b79e3e947, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF