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README.md std3n95k5ag: specified limits as data (metadata.characteristics, 28 rows from the datasheet) · Ray 17d ago
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STD3N95K5AG

STMicroelectronics · MOSFETs · DPAK

STD3N95K5AG from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate of the MOSFET, with gate-source voltage rated ±30 V (VGS) in the absolute maximum ratings.
2 D passive Drain of the MOSFET, also connected to the TAB; rated for VDS of 950 V and 2 A continuous drain current at TC = 25 °C.
3 S passive Source of the MOSFET; the source-drain diode is rated 2 A continuous and 3 A pulsed.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DPAK
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate-source voltage VGS -30 30 V 2
Drain current (continuous) at TC = 25 °C ID 2 A TC = 25 °C 2
Drain current (continuous) at TC = 100 °C ID 1.3 A TC = 100 °C 2
Drain current pulsed IDM 3 A Pulse width limited by safe operating area 2
Total power dissipation at TC = 25 °C PTOT 45 W TC = 25 °C 2
Peak diode recovery voltage slope dv/dt 4.5 V/ns ISD ≤ 2 A, di/dt ≤ 100 A/μs, VDS (peak) ≤ V(BR)DSS 2
MOSFET dv/dt ruggedness dv/dt 50 V/ns VDS ≤ 760 V 2
Operating junction temperature range Tj -55 150 °C 2
Thermal resistance, junction-to-case RthJC 2.78 °C/W 2
Thermal resistance, junction-to-board RthJB 50 °C/W When mounted on 1 inch² FR-4, 2 Oz copper board 2
Avalanche current, repetitive or not repetitive IAR 1 A Pulse width limited by TJ max. 2
Single pulse avalanche energy EAS 50 mJ Starting TJ = 25 °C, ID = IAR, VDD = 50 V 2
Drain-source breakdown voltage V(BR)DSS 950 V VGS = 0 V, ID = 1 mA 3
Zero gate voltage drain current IDSS 1 µA VDS = 950 V, VGS = 0 V 3
Zero gate voltage drain current (TC = 125 °C, defined by design) IDSS 50 µA VDS = 950 V, VGS = 0 V, TC = 125 °C 3
Gate body leakage current IGSS -10 10 µA VGS = ±20 V, VDS = 0 V 3
Gate threshold voltage VGS(th) 3 4 5 V VDS = VGS, ID = 100 µA 3
Static drain-source on-resistance RDS(on) 4.3 5 Ω VGS = 10 V, ID = 1 A 3
Source-drain current ISD 2 A 4
Source-drain current (pulsed) ISDM 3 A Pulse width limited by safe operating area 4
Forward on voltage VSD 1.5 V ISD = 2 A, VGS = 0 V (pulsed: pulse duration = 300 µs, duty cycle 1.5%) 4
Reverse recovery time trr 300 ns ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V 4
Reverse recovery charge Qrr 1.15 µC ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V 4
Reverse recovery current IRRM 7.6 A ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V 4
Reverse recovery time (TJ = 150 °C) trr 525 ns ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C 4
Reverse recovery charge (TJ = 150 °C) Qrr 1.9 µC ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C 4
Reverse recovery current (TJ = 150 °C) IRRM 7.2 A ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V, TJ = 150 °C 4
Gate-source breakdown voltage V(BR)GSO -30 30 V IGS = ±1 mA, ID = 0 A 4

CAD (KiCad official)

  • Symbol: STD3N95K5AG
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: DPAK (KiCad packages3D, STEP)
  • 3D model files: std3n95k5ag-etched.step / std3n95k5ag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); std3n95k5ag.step / std3n95k5ag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (15 pp, sha256 80bddfb7f81c41f0, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF