STC15F2K60S2-28I-PDIP40

{
  "slug": "stc15f2k60s2-28i-pdip40",
  "version": "0.1.0",
  "type": "component",
  "description": "STC Micro Microcontroller Units (MCUs/MPUs/SOCs), DIP-40. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "stc15f2k60s2-28i-pdip40",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "stc15f2k60s2-28i-pdip40.kicad_sym",
    "stc15f2k60s2-28i-pdip40.kicad_mod",
    "stc15f2k60s2-28i-pdip40.glb",
    "stc15f2k60s2-28i-pdip40.step",
    "stc15f2k60s2-28i-pdip40.lbr",
    "docs/hero.png",
    "docs/stc15f2k60s2-28i-pdip40-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "stc15f2k60s2-28i-pdip40-hero.glb",
    "stc15f2k60s2-28i-pdip40-hero.overlay.json",
    "stc15f2k60s2-28i-pdip40-etched.glb"
  ],
  "component": {
    "mpn": "STC15F2K60S2-28I-PDIP40",
    "manufacturer": "STC Micro",
    "package": "DIP-40",
    "pin_count": 40,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontroller Units (MCUs/MPUs/SOCs)",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/1f35031d9eb541258237233603be0f0b.pdf",
    "parts": {
      "symbol": "stc15f2k60s2-28i-pdip40.kicad_sym",
      "footprint": "stc15f2k60s2-28i-pdip40.kicad_mod",
      "model_3d": "stc15f2k60s2-28i-pdip40-hero.glb",
      "model_3d_plain": "stc15f2k60s2-28i-pdip40-etched.glb",
      "model_3d_step": "stc15f2k60s2-28i-pdip40-etched.step",
      "model_3d_step_plain": "stc15f2k60s2-28i-pdip40.step",
      "lbr": "stc15f2k60s2-28i-pdip40.lbr"
    },
    "distributor_links": {
      "lcsc": "C57308"
    },
    "distributor_check": {
      "checked_at": "2026-10-25T09:30:21Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "P0.0/AD0",
        "type": "bidirectional",
        "description": "Port 0 bit 0 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD0 when the external bus is used."
      },
      {
        "number": "2",
        "name": "P0.1/AD1",
        "type": "bidirectional",
        "description": "Port 0 bit 1 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD1 when the external bus is used."
      },
      {
        "number": "3",
        "name": "P0.2/AD2",
        "type": "bidirectional",
        "description": "Port 0 bit 2 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD2 when the external bus is used."
      },
      {
        "number": "4",
        "name": "P0.3/AD3",
        "type": "bidirectional",
        "description": "Port 0 bit 3 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD3 when the external bus is used."
      },
      {
        "number": "5",
        "name": "P0.4/AD4",
        "type": "bidirectional",
        "description": "Port 0 bit 4 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD4 when the external bus is used."
      },
      {
        "number": "6",
        "name": "P0.5/AD5",
        "type": "bidirectional",
        "description": "Port 0 bit 5 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD5 when the external bus is used."
      },
      {
        "number": "7",
        "name": "P0.6/AD6",
        "type": "bidirectional",
        "description": "Port 0 bit 6 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD6 when the external bus is used."
      },
      {
        "number": "8",
        "name": "P0.7/AD7",
        "type": "bidirectional",
        "description": "Port 0 bit 7 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD7 when the external bus is used."
      },
      {
        "number": "9",
        "name": "P1.0/ADC0/CCP1/RxD2",
        "type": "bidirectional",
        "description": "Port 1 bit 0 is a standard I/O that also serves as ADC input channel 0, CCP1 capture/PWM output, and UART2 receive input RxD2."
      },
      {
        "number": "10",
        "name": "P1.1/ADC1/CCP0/TxD2",
        "type": "bidirectional",
        "description": "Port 1 bit 1 is a standard I/O that also serves as ADC input channel 1, CCP0 capture/PWM output, and UART2 transmit output TxD2."
      },
      {
        "number": "11",
        "name": "P1.2/ADC2/SS/ECI",
        "type": "bidirectional",
        "description": "Port 1 bit 2 is a standard I/O that also serves as ADC input channel 2, SPI slave select SS, and the external pulse input ECI for CCP/PCA."
      },
      {
        "number": "12",
        "name": "P1.3/ADC3/MOSI",
        "type": "bidirectional",
        "description": "Port 1 bit 3 is a standard I/O that also serves as ADC input channel 3 and the SPI master-out/slave-in signal MOSI."
      },
      {
        "number": "13",
        "name": "P1.4/ADC4/MISO",
        "type": "bidirectional",
        "description": "Port 1 bit 4 is a standard I/O that also serves as ADC input channel 4 and the SPI master-in/slave-out signal MISO."
      },
      {
        "number": "14",
        "name": "P1.5/ADC5/SCLK",
        "type": "bidirectional",
        "description": "Port 1 bit 5 is a standard I/O that also serves as ADC input channel 5 and the SPI clock signal SCLK."
      },
      {
        "number": "15",
        "name": "P1.6/ADC6/RxD_3/XTAL2",
        "type": "bidirectional",
        "description": "Port 1 bit 6 is a standard I/O that also serves as ADC input channel 6, UART1 alternate receive RxD_3, and XTAL2 (output of the internal clock inverting amplifier, left floating when an external clock drives XTAL1)."
      },
      {
        "number": "16",
        "name": "P1.7/ADC7/TxD_3/XTAL1",
        "type": "bidirectional",
        "description": "Port 1 bit 7 is a standard I/O that also serves as ADC input channel 7, UART1 alternate transmit TxD_3, and XTAL1 (input of the internal clock inverting amplifier, or the external clock input when an external clock source is used)."
      },
      {
        "number": "17",
        "name": "P5.4/RST/MCLKO/SS_3",
        "type": "bidirectional",
        "description": "Port 5 bit 4 is a standard I/O (default after factory shipment) that can be set by STC-ISP to the active-high reset input RST, and also serves as master clock output MCLKO (MCLK/1, /2 or /4) and SPI alternate slave select SS_3."
      },
      {
        "number": "18",
        "name": "Vcc",
        "type": "power_in",
        "description": "Positive power supply pin for the device (5.5 V to 3.8 V for the F-series, 2.4 V to 3.6 V for the L-series)."
      },
      {
        "number": "19",
        "name": "P5.5",
        "type": "bidirectional",
        "description": "Port 5 bit 5 is a standard I/O pin (PORT5[5])."
      },
      {
        "number": "20",
        "name": "Gnd",
        "type": "power_in",
        "description": "Power supply ground pin (negative supply, connected to earth ground)."
      },
      {
        "number": "21",
        "name": "P3.0/RxD/INT4/T2CLKO",
        "type": "bidirectional",
        "description": "Port 3 bit 0 is a standard I/O that also serves as UART1 receive RxD, external interrupt INT4 (falling edge only, supports power-down wake-up), and the T2 clock output T2CLKO."
      },
      {
        "number": "22",
        "name": "P3.1/TxD/T2",
        "type": "bidirectional",
        "description": "Port 3 bit 1 is a standard I/O that also serves as UART1 transmit TxD and the external input of Timer/Counter 2 (T2)."
      },
      {
        "number": "23",
        "name": "P3.2/INT0",
        "type": "bidirectional",
        "description": "Port 3 bit 2 is a standard I/O that also serves as external interrupt INT0, which is rising- and falling-edge triggered unless IT0 is set (then falling edge only), and supports power-down wake-up."
      },
      {
        "number": "24",
        "name": "P3.3/INT1",
        "type": "bidirectional",
        "description": "Port 3 bit 3 is a standard I/O that also serves as external interrupt INT1, which is rising- and falling-edge triggered unless IT1 is set (then falling edge only), and supports power-down wake-up."
      },
      {
        "number": "25",
        "name": "P3.4/T0/T1CLKO/ECI_2",
        "type": "bidirectional",
        "description": "Port 3 bit 4 is a standard I/O that also serves as the external input of Timer/Counter 0 (T0), the Timer 1 clock output T1CLKO, and the CCP/PCA external pulse input ECI_2."
      },
      {
        "number": "26",
        "name": "P3.5/T1/T0CLKO/CCP0_2",
        "type": "bidirectional",
        "description": "Port 3 bit 5 is a standard I/O that also serves as the external input of Timer/Counter 1 (T1), the Timer 0 clock output T0CLKO, and CCP0 capture/compare/PWM channel 0 (CCP0_2)."
      },
      {
        "number": "27",
        "name": "P3.6/INT2/RxD_2/CCP1_2",
        "type": "bidirectional",
        "description": "Port 3 bit 6 is a standard I/O that also serves as external interrupt INT2 (falling edge only, supports power-down wake-up), alternate UART1 receive RxD_2, and CCP1 channel (CCP1_2)."
      },
      {
        "number": "28",
        "name": "P3.7/INT3/TxD_2/CCP2",
        "type": "bidirectional",
        "description": "Port 3 bit 7 is a standard I/O that also serves as external interrupt INT3 (falling edge only, supports power-down wake-up), alternate UART1 transmit TxD_2, and CCP2 channel (CCP2/CCP2_2)."
      },
      {
        "number": "29",
        "name": "P4.1/MISO_3",
        "type": "bidirectional",
        "description": "Port 4 bit 1 is a standard I/O that also serves as the alternate SPI master-in/slave-out signal MISO_3."
      },
      {
        "number": "30",
        "name": "P4.2/WR",
        "type": "bidirectional",
        "description": "Port 4 bit 2 is a standard I/O that also serves as the external data memory write strobe WR."
      },
      {
        "number": "31",
        "name": "P4.4/RD",
        "type": "bidirectional",
        "description": "Port 4 bit 4 is a standard I/O that also serves as the external data memory read strobe RD."
      },
      {
        "number": "32",
        "name": "P2.0/A8/RSTOUT_LOW",
        "type": "bidirectional",
        "description": "Port 2 bit 0 is a standard I/O that also serves as address bus bit A8 and RSTOUT_LOW, which outputs low from power-on and during reset until software changes it."
      },
      {
        "number": "33",
        "name": "P2.1/A9/SCLK_2",
        "type": "bidirectional",
        "description": "Port 2 bit 1 is a standard I/O that also serves as address bus bit A9 and the alternate SPI clock SCLK_2."
      },
      {
        "number": "34",
        "name": "P2.2/A10/MISO_2",
        "type": "bidirectional",
        "description": "Port 2 bit 2 is a standard I/O that also serves as address bus bit A10 and the alternate SPI master-in/slave-out MISO_2."
      },
      {
        "number": "35",
        "name": "P2.3/A11/MOSI_2",
        "type": "bidirectional",
        "description": "Port 2 bit 3 is a standard I/O that also serves as address bus bit A11 and the alternate SPI master-out/slave-in MOSI_2."
      },
      {
        "number": "36",
        "name": "P2.4/A12/ECI_3/SS_2",
        "type": "bidirectional",
        "description": "Port 2 bit 4 is a standard I/O that also serves as address bus bit A12, the alternate CCP/PCA external pulse input ECI_3, and the alternate SPI slave select SS_2."
      },
      {
        "number": "37",
        "name": "P2.5/A13/CCP0_3",
        "type": "bidirectional",
        "description": "Port 2 bit 5 is a standard I/O that also serves as address bus bit A13 and CCP0 capture/compare/PWM channel 0 (CCP0_3)."
      },
      {
        "number": "38",
        "name": "P2.6/A14/CCP1_3",
        "type": "bidirectional",
        "description": "Port 2 bit 6 is a standard I/O that also serves as address bus bit A14 and CCP1 capture/compare/PWM channel 1 (CCP1_3)."
      },
      {
        "number": "39",
        "name": "P2.7/A15/CCP2_3",
        "type": "bidirectional",
        "description": "Port 2 bit 7 is a standard I/O that also serves as address bus bit A15 and CCP2 capture/compare/PWM channel 2 (CCP2_3)."
      },
      {
        "number": "40",
        "name": "P4.5/ALE",
        "type": "bidirectional",
        "description": "Port 4 bit 5 is a standard I/O that also serves as the address latch enable output ALE."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The PDIP40 pin-number column was taken from the pin-description table (the PDIP40 column of the 1.1.; The pin-description table prints pin 7 as 'P0.6/AD5' in one row; the pin name is taken as P0.6/AD6 f; The datasheet specifies no electrical limits for this package in the extracted text, so no spec valu"
        ],
        "pages_sent": 132,
        "cost_usd": 1.0996,
        "at": "2026-10-25T09:30:04"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/1f35031d9eb541258237233603be0f0b.pdf",
        "pages": 1163,
        "sha256": "e51f2a7c23577f5f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 40,
        "described": 40,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "stc15f2k60s2-28i-pdip40.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          25.4,
          50.8,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.127,
        "footprint_binding": "identity",
        "sha256": "114010029e96b840de5e76a4e7f09f46a19e6db723f6d096bd70dbeb8ce0aff9",
        "checked": "2026-10-25",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "stc15f2k60s2-28i-pdip40-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          25.4,
          50.8,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.127,
        "footprint_binding": "identity",
        "sha256": "8c91933b3279196b908d3ab0dfdc6ab462e67d4faaaa430ab86ea34cf5bc4130",
        "checked": "2026-10-25",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}