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STC15F2K60S2-28I-PDIP40
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STC Micro Microcontroller Units (MCUs/MPUs/SOCs), DIP-40. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
Schematic Symbol
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Contents
README
markdownSTC15F2K60S2-28I-PDIP40
STC Micro · Microcontroller Units (MCUs/MPUs/SOCs) · DIP-40
STC15F2K60S2-28I-PDIP40 from STC Micro, in a DIP-40. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.0/AD0 | bidirectional | Port 0 bit 0 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD0 when the external bus is used. |
| 2 | P0.1/AD1 | bidirectional | Port 0 bit 1 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD1 when the external bus is used. |
| 3 | P0.2/AD2 | bidirectional | Port 0 bit 2 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD2 when the external bus is used. |
| 4 | P0.3/AD3 | bidirectional | Port 0 bit 3 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD3 when the external bus is used. |
| 5 | P0.4/AD4 | bidirectional | Port 0 bit 4 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD4 when the external bus is used. |
| 6 | P0.5/AD5 | bidirectional | Port 0 bit 5 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD5 when the external bus is used. |
| 7 | P0.6/AD6 | bidirectional | Port 0 bit 6 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD6 when the external bus is used. |
| 8 | P0.7/AD7 | bidirectional | Port 0 bit 7 is a general I/O (quasi-bidirectional with weak pull-up after reset, configurable to push-pull, input-only or open-drain) and doubles as address/data bus line AD7 when the external bus is used. |
| 9 | P1.0/ADC0/CCP1/RxD2 | bidirectional | Port 1 bit 0 is a standard I/O that also serves as ADC input channel 0, CCP1 capture/PWM output, and UART2 receive input RxD2. |
| 10 | P1.1/ADC1/CCP0/TxD2 | bidirectional | Port 1 bit 1 is a standard I/O that also serves as ADC input channel 1, CCP0 capture/PWM output, and UART2 transmit output TxD2. |
| 11 | P1.2/ADC2/SS/ECI | bidirectional | Port 1 bit 2 is a standard I/O that also serves as ADC input channel 2, SPI slave select SS, and the external pulse input ECI for CCP/PCA. |
| 12 | P1.3/ADC3/MOSI | bidirectional | Port 1 bit 3 is a standard I/O that also serves as ADC input channel 3 and the SPI master-out/slave-in signal MOSI. |
| 13 | P1.4/ADC4/MISO | bidirectional | Port 1 bit 4 is a standard I/O that also serves as ADC input channel 4 and the SPI master-in/slave-out signal MISO. |
| 14 | P1.5/ADC5/SCLK | bidirectional | Port 1 bit 5 is a standard I/O that also serves as ADC input channel 5 and the SPI clock signal SCLK. |
| 15 | P1.6/ADC6/RxD_3/XTAL2 | bidirectional | Port 1 bit 6 is a standard I/O that also serves as ADC input channel 6, UART1 alternate receive RxD_3, and XTAL2 (output of the internal clock inverting amplifier, left floating when an external clock drives XTAL1). |
| 16 | P1.7/ADC7/TxD_3/XTAL1 | bidirectional | Port 1 bit 7 is a standard I/O that also serves as ADC input channel 7, UART1 alternate transmit TxD_3, and XTAL1 (input of the internal clock inverting amplifier, or the external clock input when an external clock source is used). |
| 17 | P5.4/RST/MCLKO/SS_3 | bidirectional | Port 5 bit 4 is a standard I/O (default after factory shipment) that can be set by STC-ISP to the active-high reset input RST, and also serves as master clock output MCLKO (MCLK/1, /2 or /4) and SPI alternate slave select SS_3. |
| 18 | Vcc | power_in | Positive power supply pin for the device (5.5 V to 3.8 V for the F-series, 2.4 V to 3.6 V for the L-series). |
| 19 | P5.5 | bidirectional | Port 5 bit 5 is a standard I/O pin (PORT5[5]). |
| 20 | Gnd | power_in | Power supply ground pin (negative supply, connected to earth ground). |
| 21 | P3.0/RxD/INT4/T2CLKO | bidirectional | Port 3 bit 0 is a standard I/O that also serves as UART1 receive RxD, external interrupt INT4 (falling edge only, supports power-down wake-up), and the T2 clock output T2CLKO. |
| 22 | P3.1/TxD/T2 | bidirectional | Port 3 bit 1 is a standard I/O that also serves as UART1 transmit TxD and the external input of Timer/Counter 2 (T2). |
| 23 | P3.2/INT0 | bidirectional | Port 3 bit 2 is a standard I/O that also serves as external interrupt INT0, which is rising- and falling-edge triggered unless IT0 is set (then falling edge only), and supports power-down wake-up. |
| 24 | P3.3/INT1 | bidirectional | Port 3 bit 3 is a standard I/O that also serves as external interrupt INT1, which is rising- and falling-edge triggered unless IT1 is set (then falling edge only), and supports power-down wake-up. |
| 25 | P3.4/T0/T1CLKO/ECI_2 | bidirectional | Port 3 bit 4 is a standard I/O that also serves as the external input of Timer/Counter 0 (T0), the Timer 1 clock output T1CLKO, and the CCP/PCA external pulse input ECI_2. |
| 26 | P3.5/T1/T0CLKO/CCP0_2 | bidirectional | Port 3 bit 5 is a standard I/O that also serves as the external input of Timer/Counter 1 (T1), the Timer 0 clock output T0CLKO, and CCP0 capture/compare/PWM channel 0 (CCP0_2). |
| 27 | P3.6/INT2/RxD_2/CCP1_2 | bidirectional | Port 3 bit 6 is a standard I/O that also serves as external interrupt INT2 (falling edge only, supports power-down wake-up), alternate UART1 receive RxD_2, and CCP1 channel (CCP1_2). |
| 28 | P3.7/INT3/TxD_2/CCP2 | bidirectional | Port 3 bit 7 is a standard I/O that also serves as external interrupt INT3 (falling edge only, supports power-down wake-up), alternate UART1 transmit TxD_2, and CCP2 channel (CCP2/CCP2_2). |
| 29 | P4.1/MISO_3 | bidirectional | Port 4 bit 1 is a standard I/O that also serves as the alternate SPI master-in/slave-out signal MISO_3. |
| 30 | P4.2/WR | bidirectional | Port 4 bit 2 is a standard I/O that also serves as the external data memory write strobe WR. |
| 31 | P4.4/RD | bidirectional | Port 4 bit 4 is a standard I/O that also serves as the external data memory read strobe RD. |
| 32 | P2.0/A8/RSTOUT_LOW | bidirectional | Port 2 bit 0 is a standard I/O that also serves as address bus bit A8 and RSTOUT_LOW, which outputs low from power-on and during reset until software changes it. |
| 33 | P2.1/A9/SCLK_2 | bidirectional | Port 2 bit 1 is a standard I/O that also serves as address bus bit A9 and the alternate SPI clock SCLK_2. |
| 34 | P2.2/A10/MISO_2 | bidirectional | Port 2 bit 2 is a standard I/O that also serves as address bus bit A10 and the alternate SPI master-in/slave-out MISO_2. |
| 35 | P2.3/A11/MOSI_2 | bidirectional | Port 2 bit 3 is a standard I/O that also serves as address bus bit A11 and the alternate SPI master-out/slave-in MOSI_2. |
| 36 | P2.4/A12/ECI_3/SS_2 | bidirectional | Port 2 bit 4 is a standard I/O that also serves as address bus bit A12, the alternate CCP/PCA external pulse input ECI_3, and the alternate SPI slave select SS_2. |
| 37 | P2.5/A13/CCP0_3 | bidirectional | Port 2 bit 5 is a standard I/O that also serves as address bus bit A13 and CCP0 capture/compare/PWM channel 0 (CCP0_3). |
| 38 | P2.6/A14/CCP1_3 | bidirectional | Port 2 bit 6 is a standard I/O that also serves as address bus bit A14 and CCP1 capture/compare/PWM channel 1 (CCP1_3). |
| 39 | P2.7/A15/CCP2_3 | bidirectional | Port 2 bit 7 is a standard I/O that also serves as address bus bit A15 and CCP2 capture/compare/PWM channel 2 (CCP2_3). |
| 40 | P4.5/ALE | bidirectional | Port 4 bit 5 is a standard I/O that also serves as the address latch enable output ALE. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | DIP-40 |
| Category | Embedded Processors & Controllers |
| Pins | 40 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TST | -55 | 125 | ℃ | 1095 | ||
| Operating temperature (I) | TA | -40 | 85 | ℃ | 1095 | ||
| DC power supply (5V) | VDD - VSS | -0.3 | 5.5 | V | 1095 | ||
| Voltage on any pin | -0.3 | V | 1095 | ||||
| Operating Voltage | VDD | 3.3 | 5 | 5.5 | V | 1095 | |
| Operating Current | ICC | 4 | 20 | mA | 5V | 1095 | |
| Input Low (P0,P1,P2,P3) | VIL1 | 0.8 | V | 5V | 1095 | ||
| Input High (P0,P1,P2,P3) | VIH1 | 2 | V | 5V | 1095 | ||
| Input High (RESET) | VIH2 | 2.2 | V | 5V | 1095 | ||
| Sourcing Current for output high (P0,P1,P2,P3) (Quasi-output) | IOH1 | 200 | 270 | uA | 5V | 1095 | |
| Logic 0 input current (P0,P1,P2,P3) | IIL | 50 | uA | Vpin=0V | 1095 | ||
| Logic 1 to 0 transition current (P0,P1,P2,P3) | ITL | 100 | 270 | 600 | uA | Vpin=2.0V | 1095 |
| Power Down Current | IPD | 0.1 | uA | 5V | 1095 | ||
| Idle Current | IIDL | 3 | mA | 5V | 1095 | ||
| Sink Current for output low (P0,P1,P2,P3) | IOL1 | 20 | mA | 5V@Vpin=0.45V | 1095 | ||
| Sourcing Current for output high (P0,P1,P2,P3) (Push-Pull, Strong-output) | IOH2 | 20 | mA | 5V@Vpin=2.4V | 1095 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the | 422 |
CAD (KiCad official)
- Symbol:
STC15F2K60S2-28I-PDIP40 - Footprint:
Package_DIP:DIP-40_W25.4mm - 3D model: DIP-40 (KiCad packages3D, STEP)
- 3D model files:
stc15f2k60s2-28i-pdip40-etched.step/stc15f2k60s2-28i-pdip40-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc15f2k60s2-28i-pdip40.step/stc15f2k60s2-28i-pdip40.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1163 pp, sha256
e51f2a7c23577f5f, retrieved 2026-10-25, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).