component
STB14NM50N
Public Made by Adomby adom
STMicroelectronics MOSFETs, D2PAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTB14NM50N
STMicroelectronics · MOSFETs · D2PAK
STB14NM50N from STMicroelectronics, in a D2PAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate terminal of the N-channel MOSFET; gate-source voltage is rated at ±25 V (Table 1, page 2). |
| 2 | D | passive | Drain terminal, electrically connected to the tab; drain-source voltage is rated at 500 V and continuous drain current at TC = 25 °C is 12 A (Table 1, page 2). |
| 3 | S | passive | Source terminal, the reference for VGS; the source-drain diode is rated at 12 A continuous and 48 A pulsed (Table 7, page 4). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | D2PAK |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | 500 | V | 2 | |||
| Gate-source voltage | VGS | -25 | 25 | V | 2 | ||
| Drain current (continuous) | ID | 12 | A | TC = 25 °C | 2 | ||
| Drain current (continuous) | ID | 8 | A | TC = 100 °C | 2 | ||
| Drain current (pulsed) | IDM | 48 | A | Pulse width limited by safe operating area | 2 | ||
| Total power dissipation | PTOT | 90 | W | TC = 25 °C | 2 | ||
| Peak diode recovery voltage slope | dv/dt | 15 | V/ns | ISD ≤ 12 A, di/dt ≤ 400 A/μs, VDS (peak) ≤ V(BR)DSS, VDD = 80% V(BR)DSS | 2 | ||
| Operating junction temperature range | TJ | -55 | 150 | °C | 2 | ||
| Thermal resistance, junction-to-case | RthJC | 1.39 | °C/W | 2 | |||
| Thermal resistance, junction-to-ambient | RthJA | 30 | °C/W | When mounted on a standard 1 inch² area of FR-4 PCB with 2-oz copper | 2 | ||
| Avalanche current, repetitive or not-repetitive | IAR | 4 | A | Pulse width limited by TJ max. | 2 | ||
| Single pulse avalanche energy | EAS | 172 | mJ | Starting TJ = 25 °C, ID = IAR, VDD = 50 V | 2 | ||
| Drain-source breakdown voltage | V(BR)DSS | 500 | V | ID = 1 mA, VGS = 0 V | 3 | ||
| Zero gate voltage drain current | IDSS | 1 | µA | VGS = 0 V, VDS = 500 V | 3 | ||
| Zero gate voltage drain current (TC = 125 °C) | IDSS | 100 | µA | VGS = 0 V, VDS = 500 V, TC = 125 °C (specified by design, not tested in production) | 3 | ||
| Gate body leakage current | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ±20 V | 3 | |
| Gate threshold voltage | VGS(th) | 2 | 3 | 4 | V | VDS = VGS, ID = 250 µA | 3 |
| Static drain-source on-resistance | RDS(on) | 285 | 320 | mΩ | VGS = 10 V, ID = 6 A | 3 | |
| Source-drain current | ISD | 12 | A | 4 | |||
| Source-drain current (pulsed) | ISDM | 48 | A | Pulse width limited by safe operating area | 4 | ||
| Forward on voltage | VSD | 1.6 | V | ISD = 12 A, VGS = 0 V | 4 |
CAD (KiCad official)
- Symbol:
STB14NM50N - Footprint:
Package_TO_SOT_SMD:TO-263-2 - 3D model: D2PAK (KiCad packages3D, STEP)
- 3D model files:
stb14nm50n-etched.step/stb14nm50n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stb14nm50n.step/stb14nm50n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (13 pp, sha256
afbae22f7b63e4e7, retrieved 2026-10-09, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).