# STB11N65M5

**STMicroelectronics** · MOSFETs · D2PAK

STB11N65M5 from STMicroelectronics, in a D2PAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate terminal; gate-source voltage is limited to ±25 V (Table 1), with gate threshold VGS(th) of 3 to 5 V at ID = 250 µA (Table 4). |
| 2 | D | passive | Drain terminal, electrically connected to the TAB; drain-source breakdown V(BR)DSS is 650 V minimum and continuous drain current is 9 A at TC = 25 °C (Tables 1 and 4). |
| 3 | S | passive | Source terminal; source-drain diode forward voltage VSD is 1.5 V maximum at ISD = 9 A, VGS = 0 V (Table 7). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | D2PAK |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate-source voltage | VGS | -25 |  | 25 | V |  | 2 |
| Drain current (continuous) | ID |  |  | 9 | A | TC = 25 °C | 2 |
| Drain current (continuous) | ID |  |  | 5.6 | A | TC = 100 °C | 2 |
| Drain current (pulsed) | IDM |  |  | 36 | A | Pulse width limited by safe operating area | 2 |
| Total power dissipation | PTOT |  |  | 85 | W | TC = 25 °C | 2 |
| Peak diode recovery voltage slope | dv/dt |  |  | 15 | V/ns | ISD ≤ 9 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V | 2 |
| Operating junction temperature range | TJ | -55 |  | 150 | °C |  | 2 |
| Avalanche current, repetitive or not-repetitive | IAR |  |  | 2 | A | Pulse width limited by TJ max. | 2 |
| Single pulse avalanche energy | EAS |  |  | 130 | mJ | Starting Tj = 25 °C, ID = IAR, VDD = 50 V | 2 |
| Thermal resistance, junction-to-case | RthJC |  | 1.47 |  | °C/W | D2PAK | 2 |
| Thermal resistance, junction-to-ambient | RthJA |  | 30 |  | °C/W | Mounted on a standard 1 inch² area of FR-4 PCB with 2-oz copper (D2PAK) | 2 |
| Drain-source breakdown voltage | V(BR)DSS | 650 |  |  | V | ID = 1 mA, VGS = 0 V | 3 |
| Zero gate voltage drain current | IDSS |  |  | 1 | µA | VGS = 0 V, VDS = 650 V | 3 |
| Zero gate voltage drain current | IDSS |  |  | 100 | µA | VGS = 0 V, VDS = 650 V, TC = 125 °C (specified by design, not tested in production) | 3 |
| Gate body leakage current | IGSS | -100 |  | 100 | nA | VDS = 0 V, VGS = ±25 V | 3 |
| Gate threshold voltage | VGS(th) | 3 | 4 | 5 | V | VDS = VGS, ID = 250 µA | 3 |
| Static drain-source on resistance | RDS(on) |  | 430 | 480 | mΩ | VGS = 10 V, ID = 4.5 A | 3 |
| Source-drain current | ISD |  |  | 9 | A |  | 4 |
| Source-drain current (pulsed) | ISDM |  |  | 36 | A | Pulse width limited by safe operating area | 4 |
| Forward on voltage | VSD |  |  | 1.5 | V | ISD = 9 A, VGS = 0 V | 4 |

## CAD (KiCad official)

- Symbol: `STB11N65M5`
- Footprint: `Package_TO_SOT_SMD:TO-263-2`
- 3D model: D2PAK (KiCad packages3D, STEP)
- 3D model files: `stb11n65m5-etched.step` / `stb11n65m5-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stb11n65m5.step` / `stb11n65m5.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stb11n65m5.pdf) (29 pp, sha256 `969b562ca35a0d73`, retrieved 2026-10-12, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stb11n65m5-datasheet.pdf)