component
ST25DV64KC-IE8T3
Public Made by Adomby adom
STMicroelectronics RF Chips, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ST25DV64KC-IE8T3
STMicroelectronics · RF Chips · TSSOP-8
ST25DV64KC-IE8T3 from STMicroelectronics, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | V_EH | power_out | Energy harvesting analog output pin used to power external components. |
| 2 | AC0 | passive | Antenna coil connection AC0 for the RF interface. |
| 3 | AC1 | passive | Antenna coil connection AC1 for the RF interface. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Serial data I/O of the two-wire I2C interface (up to 1 MHz protocol). |
| 6 | SCL | input | Serial clock input of the two-wire I2C interface. |
| 7 | GPO | output | Interrupt output, open-drain on this IE version; it is released (high impedance) when not driven and needs an external pull-up. |
| 8 | VCC | power_in | Supply voltage input; the device operates from a single supply of 1.8 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-8 |
| Category | Radio Frequency Chip/Antenna |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient operating temperature (RF interface, SO8N/TSSOP8) | TA | -40 | 105 | °C | Range 8; SO8N, TSSOP; RF interface | 141 | |
| Ambient operating temperature (I2C interface, SO8N/TSSOP8) | TA | -40 | 125 | °C | Range 8; SO8N, TSSOP; I2C interface | 141 | |
| Storage temperature | TSTG | -65 | 150 | °C | UFDFPN8, SO8N, TSSOP8, UFDFPN12, WLCSP10 | 141 | |
| I2C input or output range | VIO | -0.5 | 6.5 | V | 141 | ||
| I2C supply voltage | VCC | -0.5 | 6.5 | V | 141 | ||
| DC output current on pin SDA (when equal to 0) | IOL_MAX_SDA | 5 | mA | when equal to 0 | 141 | ||
| DC output current on pin GPO (when equal to 0) | IOL_MAX_GPO | 1.5 | mA | when equal to 0 | 141 | ||
| RF input voltage amplitude peak to peak between AC0 and AC1 | VMAX_1 | 11 | V | VAC0 - VAC1; VSS pin left floating | 141 | ||
| AC voltage between AC0 and VSS, or AC1 and VSS | VMAX_2 | -0.5 | 5.5 | V | VAC0 - VSS, or VAC1 - VSS | 141 | |
| Electrostatic discharge voltage (human body model) | VESD | 2000 | V | All pins | 141 | ||
| Supply voltage (I2C operating conditions) | VCC | 1.8 | 5.5 | V | I2C operating conditions | 142 | |
| Ambient operating temperature (I2C operating conditions) | TA | -40 | 125 | °C | Range 8; SO8N, TSSOP8 | 142 | |
| Input capacitance (SDA) | CIN | 8 | pF | Input capacitance (SDA) | 142 | ||
| Input capacitance (other pins) | CIN | 6 | pF | Input capacitance (other pins) | 142 | ||
| Pulse width ignored (input filter on SCL and SDA) | tNS | 80 | ns | Pulse width ignored (input filter on SCL and SDA) | 142 | ||
| Input leakage current (SCL, SDA) | ILI | -0.1 | 0.03 | 0.1 | µA | VIN = VSS or VCC, device in Standby mode | 144 |
| Operating supply current read (device select E2 address) | ICC_E2 | 126 | 180 | µA | VCC = 1.8 V, fC = 1MHz (rise/fall time < 50 ns) | 144 | |
| Operating supply current read (device select E2 address) | ICC_E2 | 230 | 260 | µA | VCC = 3.3 V, fC = 1MHz (rise/fall time < 50 ns) | 144 | |
| Operating supply current read (device select E2 address) | ICC_E2 | 510 | 550 | µA | VCC = 5.5 V, fC = 1MHz (rise/fall time < 50 ns) | 144 | |
| Operating supply current write (device select E2 address) | ICC0 | 120 | 220 | µA | VCC = 1.8 V, fC = 1MHz (rise/fall time < 50 ns) | 144 | |
| Operating supply current write (device select E2 address) | ICC0 | 120 | 230 | µA | VCC = 3.3 V, fC = 1MHz (rise/fall time < 50 ns) | 144 | |
| Operating supply current write (device select E2 address) | ICC0 | 140 | 260 | µA | VCC = 5.5 V, fC = 1MHz (rise/fall time < 50 ns) | 144 | |
| Operating supply current write (device select MB address) | ICC0_MB | 180 | 220 | µA | VCC = 1.8 V, fC = 1MHz (rise/fall time < 50 ns) | 144 | |
| Operating supply current write (device select MB address) | ICC0_MB | 290 | 320 | µA | VCC = 3.3 V, fC = 1MHz (rise/fall time < 50 ns) | 145 | |
| Operating supply current write (device select MB address) | ICC0_MB | 520 | 600 | µA | VCC = 5.5 V, fC = 1MHz (rise/fall time < 50 ns) | 145 | |
| Low power down supply current | ICC1 | 2.5 | 5 | µA | LPD = 1; VCC = 1.8 V | 145 | |
| Low power down supply current | ICC1 | 3 | 6 | µA | LPD = 1; VCC = 3.3 V | 145 | |
| Low power down supply current | ICC1 | 4 | 7 | µA | LPD = 1; VCC = 5.5 V | 145 | |
| Static standby supply current after power ON or device select stop or time out | ICC1_PON | 78 | 110 | µA | LPD = 0; VCC = 1.8 V | 145 | |
| Static standby supply current after power ON or device select stop or time out | ICC1_PON | 82 | 110 | µA | LPD = 0; VCC = 3.3 V | 145 | |
| Static standby supply current after power ON or device select stop or time out | ICC1_PON | 95 | 130 | µA | LPD = 0; VCC = 5.5 V | 145 | |
| Input low voltage (SDA, SCL) | VIL | -0.45 | V | VCC = 1.8 V | 145 | ||
| Input low voltage (LPD) | VIL_LPD | -0.45 | V | VCC = 3.3 V | 145 | ||
| Output low voltage SDA (1 MHz) | VOL_SDA | 0.05 | 0.4 | V | IOL = 1 mA, VCC = 1.8 V | 145 | |
| Output low voltage SDA (1 MHz) | VOL_SDA | 0.08 | 0.4 | V | IOL = 2.1 mA, VCC = 3.3 V | 145 | |
| Output low voltage SDA (1 MHz) | VOL_SDA | 0.1 | 0.4 | V | IOL = 3 mA, VCC = 5.5 V | 145 | |
| Device select acknowledge (VCC power-up) | VCC_Power_up | 1.48 | 1.7 | V | fC = 100 KHz | 145 | |
| Clock frequency | fC | 0.05 | 1000 | kHz | Test conditions specified in Table 246 | 147 | |
| Clock pulse width high | tCHCL | 0.26 | 25000 | µs | Test conditions specified in Table 246; tCHCL timeout | 147 | |
| Clock pulse width low | tCLCH | 0.5 | 25000 | µs | Test conditions specified in Table 246; tCLCH timeout | 147 | |
| I2C timeout on Start condition | tSTART_OUT | 35 | ms | Test conditions specified in Table 246 | 147 | ||
| Clock low to next data valid (access time) | tCLQV | 450 | ns | Test conditions specified in Table 246 | 147 | ||
| Start condition hold time | tDLCL | 0.25 | 35000 | µs | Test conditions specified in Table 246; tDLCL timeout | 147 | |
| I2C write time | tW | 5.5 | ms | Test conditions specified in Table 246 | 147 | ||
| Power-up boot time (RF OFF) | tboot_LPD | 0.6 | ms | RF OFF | 147 | ||
| Output low voltage (GPO open drain) | VOL_GPO_OD | 0.28 | 0.4 | V | IOL = 1 mA, VCC = 1.8 V | 149 | |
| Output low voltage (GPO open drain) | VOL_GPO_OD | 0.22 | 0.4 | V | IOL = 1 mA, VCC = 3.3 V | 149 | |
| Output low voltage (GPO open drain) | VOL_GPO_OD | 0.21 | 0.4 | V | IOL = 1 mA, VCC = 5.5 V | 149 | |
| Output leakage current (GPO open drain) | IL_GPO_OD | -0.15 | 0.06 | 0.15 | µA | GPO in Hi-Z, external voltage applied on GPO, VSS or VCC | 149 |
| External RF signal frequency | fCC | 13.553 | 13.56 | 13.567 | MHz | 150 | |
| Operating field according to ISO | H_ISO | 150 | 5000 | mA/m | Range 8 TA = -40 °C to 105 °C | 150 | |
| 10% carrier modulation index | MICARRIER | 10 | 30 | % | MI=(A-B)/(A+B); 150 mA/m > H_ISO > 1000 mA/m | 150 | |
| 100% carrier modulation index | MICARRIER | 95 | 100 | % | MI=(A-B)/(A+B) | 150 | |
| Minimum time from carrier generation to first data | tMIN CD | 1 | ms | From H-field min | 150 | ||
| Time for ST25DVxxKC response | t1 | 318.6 | 320.9 | 323.3 | µs | 4352/FC | 150 |
| RF OFF time (chip reset) | tRF_OFF | 2 | ms | Chip reset | 150 | ||
| Internal tuning capacitor | CTUN | 28.5 | pF | f = 13.56 MHz | 150 | ||
| Thermal resistance junction-ambient, TSSOP8 3 x 6.4 mm package | ƟJA | 255 | °C/W | TSSOP8 3 x 6.4 mm, 0.65 mm pitch; JEDEC JESD51-7 2s2p board | 151 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Grey color indicates the states where power is delivered on V_EH pin. | 50 |
CAD (KiCad official)
- Symbol:
ST25DV64KC-IE8T3 - Footprint:
Package_SO:TSSOP-8_4.4x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
st25dv64kc-ie8t3-etched.step/st25dv64kc-ie8t3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);st25dv64kc-ie8t3.step/st25dv64kc-ie8t3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (203 pp, sha256
aaa637577efb1a5d, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).