SS4127

{
  "schema_version": 1,
  "type": "component",
  "slug": "ss4127",
  "title": "SS4127",
  "brief": "orisilicon Leakage Protection ICs, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "power management (pmic)",
    "ss4127"
  ],
  "component": {
    "mpn": "SS4127",
    "manufacturer": "orisilicon",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Power Management (PMIC)",
    "subcategory": "Leakage Protection ICs",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603322322502250496",
    "parts": {
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      "footprint": "ss4127.kicad_mod",
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      "model_3d_plain": "ss4127.glb",
      "model_3d_step": "ss4127-etched.step",
      "model_3d_step_plain": "ss4127.step",
      "lbr": "ss4127.lbr"
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    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "IN1",
        "type": "input",
        "description": "Op-amp input 1 (leakage-sense differential input, connected to current-transformer secondary). Trip threshold |IN1 - IN2| = 4.95 mV typical."
      },
      {
        "number": "2",
        "name": "IN2",
        "type": "input",
        "description": "Op-amp input 2 (leakage-sense differential input, connected to current-transformer secondary)."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference."
      },
      {
        "number": "4",
        "name": "OA",
        "type": "output",
        "description": "Op-amp / filter output and reverse-time delay adjustment pin. External capacitor (C_OA, e.g. 33 nF) forms the integrator that generates the inverse-time trip curve; internal threshold is 1.5 V."
      },
      {
        "number": "5",
        "name": "DLY",
        "type": "output",
        "description": "Fixed-delay control pin. An external capacitor C_D to GND sets the trip delay via T_D = C_D × V_REF / I_D (V_REF = 1.5 V, I_D ≈ 3 µA). E.g. 0.8 µF → ~0.4 s; 3.42 µF → ~1.71 s."
      },
      {
        "number": "6",
        "name": "OSHV",
        "type": "output",
        "description": "High-voltage MOSFET trip driver output. Drives external high-voltage MOS gate; typical output voltage ~10 V (with VS=12V), delivers 3 pulses of 30 ms with 100 ms period on trip."
      },
      {
        "number": "7",
        "name": "OSLV",
        "type": "output",
        "description": "Low-voltage SCR (thyristor) trigger output. Typical output ~5 V (with VS=12V), source current up to ~750 µA (OS=0.8 V); provides 3 pulses of 30 ms with 100 ms period on trip."
      },
      {
        "number": "8",
        "name": "VS",
        "type": "power_in",
        "description": "Supply pin. Internal clamp/regulator: V_S1 ≈ 12 V typical (I_S = 1 mA). Absolute max VS to GND: -0.3 V to +24 V. Typical quiescent current 180 µA."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603322322502250496",
        "pages": 16,
        "sha256": "77533e6513c282e4",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ss4127-etched.step",
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        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "orisilicon",
      "Package": "SOP-8",
      "Category": "Power Management (PMIC)",
      "Pins": "8"
    }
  },
  "variants": [
    {
      "mpn": "SS4127",
      "kind": "packaging"
    }
  ],
  "sections": [
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  "discovery_triggers": [
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  "discovery_pitch": "SS4127 (orisilicon) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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    "ss4127.lbr",
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    "docs/ss4127-datasheet.pdf",
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  "visibility": {
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  "updated_at": "2026-09-25T08:06:29.371Z"
}