component

SS4127

Public Made by Adom

by adom

orisilicon Leakage Protection ICs, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)ss4127
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ss4127: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers ss4127: viewers · Ray 28d ago
package.json Publish 0.1.0 · Ray 28d ago
page.json ss4127: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 20h ago
README.md ss4127: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
ss4127-etched.fit.json ss4127: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ss4127-etched.glb ss4127: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ss4127-etched.step ss4127: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ss4127.glb Publish 0.1.0 · Ray 28d ago
ss4127.kicad_mod Publish 0.1.0 · Ray 28d ago
ss4127.kicad_sym Publish 0.1.0 · Ray 28d ago
ss4127.lbr Publish 0.1.0 · Ray 28d ago
ss4127.step Publish 0.1.0 · Ray 28d ago

SS4127

orisilicon · Leakage Protection ICs · SOP-8

SS4127 from orisilicon, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1 input Op-amp input 1 (leakage-sense differential input, connected to current-transformer secondary). Trip threshold
2 IN2 input Op-amp input 2 (leakage-sense differential input, connected to current-transformer secondary).
3 GND power_in Device ground reference.
4 OA output Op-amp / filter output and reverse-time delay adjustment pin. External capacitor (C_OA, e.g. 33 nF) forms the integrator that generates the inverse-time trip curve; internal threshold is 1.5 V.
5 DLY output Fixed-delay control pin. An external capacitor C_D to GND sets the trip delay via T_D = C_D × V_REF / I_D (V_REF = 1.5 V, I_D ≈ 3 µA). E.g. 0.8 µF → ~0.4 s; 3.42 µF → ~1.71 s.
6 OSHV output High-voltage MOSFET trip driver output. Drives external high-voltage MOS gate; typical output voltage ~10 V (with VS=12V), delivers 3 pulses of 30 ms with 100 ms period on trip.
7 OSLV output Low-voltage SCR (thyristor) trigger output. Typical output ~5 V (with VS=12V), source current up to ~750 µA (OS=0.8 V); provides 3 pulses of 30 ms with 100 ms period on trip.
8 VS power_in Supply pin. Internal clamp/regulator: V_S1 ≈ 12 V typical (I_S = 1 mA). Absolute max VS to GND: -0.3 V to +24 V. Typical quiescent current 180 µA.

Key specifications

Parameter Value
Manufacturer orisilicon
Package SOP-8
Category Power Management (PMIC)
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • SS4127

CAD (KiCad official)

  • Symbol: SS4127
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ss4127-etched.step / ss4127-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ss4127.step / ss4127.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: orisilicon datasheet (16 pp, sha256 77533e6513c282e4, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF