component
SRK2000ATR
Public Made by Adomby adom
STMicroelectronics Supervisor And Reset ICs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SRK2000ATR
STMicroelectronics · Supervisor And Reset ICs · SO-8
SRK2000ATR from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SGND | power_in | Signal ground, return of the device bias current and 0 V reference for both drain-to-source voltage monitors, to be routed directly to PGND. |
| 2 | EN | input | Sets the drain-voltage turn-off threshold (-12 mV or -25 mV), programs the gate-driver UVLO (VEN_On 1.8 V typ.), and acts as enable, with pulling it to ground disabling GD1 and GD2. |
| 3 | DVS1 | input | Drain voltage sense for section 1, connected to the SR MOSFET drain through a limiting resistor, with analog input voltage rated -0.3 V to VCCZ and sink current limited to 25 mA. |
| 4 | DVS2 | input | Drain voltage sense for section 2, connected to the SR MOSFET drain through a limiting resistor, with analog input voltage rated -0.3 V to VCCZ and sink current limited to 25 mA. |
| 5 | GD2 | output | Gate driver output for section 2, a totem-pole stage with 1 A peak source and 3.5 A peak sink current, with high level clamped at about 12 V. |
| 6 | PGND | power_in | Power ground, return for gate drive currents, to be routed to the common point where the source terminals of both SR MOSFETs connect. |
| 7 | GD1 | output | Gate driver output for section 1, a totem-pole stage with 1 A peak source and 3.5 A peak sink current, with high level clamped at about 12 V. |
| 8 | VCC | power_in | Supply voltage of the device, with a 4.5 to 32 V operating range after turn-on and absolute maximum DC supply of -0.3 V to VCCZ, bypassed to SGND with about 0.1 µF. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SRK2000ATR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
srk2000atr-etched.step/srk2000atr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);srk2000atr.step/srk2000atr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (19 pp, sha256
b1f0f9364b7fc748, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SRK2000ATR
**STMicroelectronics** · Supervisor And Reset ICs · SO-8
SRK2000ATR from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SGND | power_in | Signal ground, return of the device bias current and 0 V reference for both drain-to-source voltage monitors, to be routed directly to PGND. |
| 2 | EN | input | Sets the drain-voltage turn-off threshold (-12 mV or -25 mV), programs the gate-driver UVLO (VEN_On 1.8 V typ.), and acts as enable, with pulling it to ground disabling GD1 and GD2. |
| 3 | DVS1 | input | Drain voltage sense for section 1, connected to the SR MOSFET drain through a limiting resistor, with analog input voltage rated -0.3 V to VCCZ and sink current limited to 25 mA. |
| 4 | DVS2 | input | Drain voltage sense for section 2, connected to the SR MOSFET drain through a limiting resistor, with analog input voltage rated -0.3 V to VCCZ and sink current limited to 25 mA. |
| 5 | GD2 | output | Gate driver output for section 2, a totem-pole stage with 1 A peak source and 3.5 A peak sink current, with high level clamped at about 12 V. |
| 6 | PGND | power_in | Power ground, return for gate drive currents, to be routed to the common point where the source terminals of both SR MOSFETs connect. |
| 7 | GD1 | output | Gate driver output for section 1, a totem-pole stage with 1 A peak source and 3.5 A peak sink current, with high level clamped at about 12 V. |
| 8 | VCC | power_in | Supply voltage of the device, with a 4.5 to 32 V operating range after turn-on and absolute maximum DC supply of -0.3 V to VCCZ, bypassed to SGND with about 0.1 µF. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `SRK2000ATR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `srk2000atr-etched.step` / `srk2000atr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `srk2000atr.step` / `srk2000atr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590162534524489728) (19 pp, sha256 `b1f0f9364b7fc748`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/srk2000atr-datasheet.pdf)