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SQ4917EY-T1_GE3

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Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SQ4917EY-T1_GE3

Vishay Intertech · MOSFETs · SO-8

SQ4917EY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of P-channel MOSFET 1 in the dual SO-8 package, rated for the device's -60 V VDS and ±20 V VGS limits.
2 G1 input Gate of P-channel MOSFET 1, with VGS limited to ±20 V per the absolute maximum ratings.
3 S2 passive Source of P-channel MOSFET 2 in the dual SO-8 package, rated for the device's -60 V VDS and ±20 V VGS limits.
4 G2 input Gate of P-channel MOSFET 2, with VGS limited to ±20 V per the absolute maximum ratings.
5 D2 passive Drain of P-channel MOSFET 2, with VDS rated at -60 V and continuous drain current of -8 A per leg (TC = 25 °C).
6 D2 passive Drain of P-channel MOSFET 2 (second drain lead of the same die), with VDS rated at -60 V and continuous drain current of -8 A per leg (TC = 25 °C).
7 D1 passive Drain of P-channel MOSFET 1 (second drain lead of the same die), with VDS rated at -60 V and continuous drain current of -8 A per leg (TC = 25 °C).
8 D1 passive Drain of P-channel MOSFET 1, with VDS rated at -60 V and continuous drain current of -8 A per leg (TC = 25 °C).

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage VDS -60 V VGS = 0 V, ID = -250 μA 2
Gate-Source Threshold Voltage VGS(th) -1.5 -2 -2.5 V VDS = VGS, ID = -250 μA 2
Gate-Source Leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero Gate Voltage Drain Current IDSS -1 μA VGS = 0 V, VDS = -60 V 2
Zero Gate Voltage Drain Current IDSS -50 μA VGS = 0 V, VDS = -60 V, TJ = 125 °C 2
Zero Gate Voltage Drain Current IDSS -150 μA VGS = 0 V, VDS = -60 V, TJ = 175 °C 2
On-State Drain Current ID(on) -30 A VGS = -10 V, VDS ≤ -5 V 2
Drain-Source On-State Resistance RDS(on) 0.04 0.048 Ω VGS = -10 V, ID = -4.3 A 2
Drain-Source On-State Resistance RDS(on) 0.078 Ω VGS = -10 V, ID = -4.3 A, TJ = 125 °C 2
Drain-Source On-State Resistance RDS(on) 0.096 Ω VGS = -10 V, ID = -4.3 A, TJ = 175 °C 2
Drain-Source On-State Resistance RDS(on) 0.051 0.0612 Ω VGS = -4.5 V, ID = -3.8 A 2
Input Capacitance Ciss 1530 1910 pF VGS = 0 V, VDS = -30 V, f = 1 MHz 2
Output Capacitance Coss 334 417 pF VGS = 0 V, VDS = -30 V, f = 1 MHz 2
Reverse Transfer Capacitance Crss 114 142 pF VGS = 0 V, VDS = -30 V, f = 1 MHz 2
Total Gate Charge Qg 43.4 65 nC VGS = -10 V, VDS = -30 V, ID = -5 A 2
Gate Resistance Rg 1.3 2.5 4 Ω f = 1 MHz 2
Turn-On Delay Time td(on) 11 17 ns VDD = -30 V, RL = 8.8 Ω, ID ≅ -5 A, VGEN = -10 V, Rg = 1 Ω 2
Rise Time tr 11 17 ns VDD = -30 V, RL = 8.8 Ω, ID ≅ -5 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-Off Delay Time td(off) 35 52 ns VDD = -30 V, RL = 8.8 Ω, ID ≅ -5 A, VGEN = -10 V, Rg = 1 Ω 2
Pulsed Current ISM -32 A 2
Forward Voltage VSD -0.8 -1.2 V IF = -2.8 A, VGS = 0 V 2
Drain-Source Voltage VDS -60 V TC = 25 °C unless otherwise noted 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID -8 A TC = 25 °C 1
Continuous Drain Current ID -4.75 A TC = 125 °C 1
Continuous Source Current (Diode Conduction) IS -4.5 A 1
Pulsed Drain Current IDM -32 A Pulse width ≤ 300 μs, duty cycle ≤ 2 % 1
Single Pulse Avalanche Current IAS -22.4 A L = 0.1 mH 1
Single Pulse Avalanche Energy EAS 25 mJ 1
Maximum Power Dissipation PD 5 W TC = 25 °C 1
Maximum Power Dissipation PD 1.67 W TC = 125 °C 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 175 °C 1
Junction-to-Ambient PCB Mount RthJA 110 °C/W PCB mount, 1" square PCB (FR-4 material) 1
Junction-to-Foot (Drain) RthJF 30 °C/W 1

CAD (KiCad official)

  • Symbol: SQ4917EY-T1_GE3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: sq4917ey-t1-ge3-etched.step / sq4917ey-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sq4917ey-t1-ge3.step / sq4917ey-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (10 pp, sha256 90b7cd3a7cabed3e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF