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SN75LVPE5421RUAR

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Texas Instruments Interface - PCIs / PCIEs, WQFN-42. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN75LVPE5421RUAR

Texas Instruments · Interface - PCIs / PCIEs · WQFN-42

SN75LVPE5421RUAR from Texas Instruments, in a WQFN-42. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GAIN/SDA bidirectional In Pin Mode this 5-level pin sets the flat broadband (DC and AC) gain for all channels and is sampled at power-up only; in SMBus/I2C mode it is the 3.3V SMBus/I2C data line and needs an external pull-up such as 4.7 kΩ.
2 RSVD1 passive Reserved pin; for best signal integrity connect it to GND, with a 0 Ω resistor to GND as an alternate option.
3 TX0P output Noninverting differential TX output for Channel 0.
4 TX0N output Inverting differential TX output for Channel 0.
5 VCC power_in Power supply, VCC = 3.3V ±10%; connect through a low-resistance path to the board VCC plane.
6 GND power_in Ground reference for the device.
7 TX1P output Noninverting differential TX output for Channel 1.
8 TX1N output Inverting differential TX output for Channel 1.
9 GND power_in Ground reference for the device.
10 TX2P output Noninverting differential TX output for Channel 2.
11 TX2N output Inverting differential TX output for Channel 2.
12 RSVD2 passive Reserved pin; for best signal integrity connect it to GND, with a 0 Ω resistor to GND as an alternate option.
13 VCC power_in Power supply, VCC = 3.3V ±10%; connect through a low-resistance path to the board VCC plane.
14 TX3P output Noninverting differential TX output for Channel 3.
15 TX3N output Inverting differential TX output for Channel 3.
16 GND power_in Ground reference for the device.
17 SEL input 3.3V LVCMOS mux select (weak internal pull-down) choosing Port A (Low) or Port B (High); it must be exercised in system implementations and is also used in the PCIe RX_DET state machine.
18 PD input 3.3V LVCMOS 2-level power-down control: High powers down all channels and Low powers up normal operation; PD must be low for a valid pulse width of at least 200 µs to be detected.
19 TEST output TI internal test pin; keep no connect.
20 EQ1 input 5-level input that, together with EQ0, sets receiver linear equalization (CTLE, AC gain) for all channels in Pin Mode; sampled at device power-up only.
21 GND power_in Ground reference for the device.
22 RXB3N input Inverting differential RX input for Port B, Channel 3.
23 RXB3P input Noninverting differential RX input for Port B, Channel 3.
24 RXA3N input Inverting differential RX input for Port A, Channel 3.
25 RXA3P input Noninverting differential RX input for Port A, Channel 3.
26 RXB2N input Inverting differential RX input for Port B, Channel 2.
27 RXB2P input Noninverting differential RX input for Port B, Channel 2.
28 RXA2N input Inverting differential RX input for Port A, Channel 2.
29 RXA2P input Noninverting differential RX input for Port A, Channel 2.
30 GND power_in Ground reference for the device.
31 RXB1N input Inverting differential RX input for Port B, Channel 1.
32 RXB1P input Noninverting differential RX input for Port B, Channel 1.
33 RXA1N input Inverting differential RX input for Port A, Channel 1.
34 RXA1P input Noninverting differential RX input for Port A, Channel 1.
35 RXB0N input Inverting differential RX input for Port B, Channel 0.
36 RXB0P input Noninverting differential RX input for Port B, Channel 0.
37 RXA0N input Inverting differential RX input for Port A, Channel 0.
38 RXA0P input Noninverting differential RX input for Port A, Channel 0.
39 GND power_in Ground reference for the device.
40 EQ0/ADDR input 5-level pin: in Pin Mode it sets receiver CTLE (AC gain) with EQ1 and is sampled at power-up only; in SMBus/I2C mode it sets the secondary address together with MODE.
41 MODE input 5-level pin that selects the control configuration: L0 is Pin Mode, L1 or L2 is SMBus/I2C mode, and L3/L4 (float) are reserved for TI internal test; sampled at power-up or in normal operation.
42 RX_DET/SCL bidirectional 5-level pin that sets receiver-detect state machine options in Pin Mode (sampled at power-up only) and is the 3.3V SMBus/I2C clock line needing an external pull-up such as 4.7 kΩ in SMBus/I2C mode.
43 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-42
Category Interface
Pins 43

CAD (KiCad official)

  • Symbol: SN75LVPE5421RUAR
  • Footprint: Package_DFN_QFN:QFN-42-1EP_5x6mm_P0.4mm_EP3.7x4.7mm
  • 3D model: WQFN-42 (KiCad packages3D, STEP)
  • 3D model files: sn75lvpe5421ruar-etched.step / sn75lvpe5421ruar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75lvpe5421ruar.step / sn75lvpe5421ruar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 11ba0b44cce0af26, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF