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SN74LVTZ244PWR

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Texas Instruments Buffer/Driver/Transceiver, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVTZ244PWR

Texas Instruments · Buffer/Driver/Transceiver · TSSOP-20

SN74LVTZ244PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for buffers 1Y1 to 1Y4; when low the 1A inputs pass to the 1Y outputs, and when high the outputs are in the high-impedance state.
2 1A1 input Data input to the first buffer of bank 1; active bus-hold holds it at a valid logic level when floating and it accepts 5.5-V input voltages with VCC at 3.3 V.
3 2Y4 tri_state Buffered output of bank 2 (from 2A4), in the high-impedance state while 2OE is high.
4 1A2 input Data input to the second buffer of bank 1; active bus-hold holds it at a valid logic level when floating and it accepts 5.5-V input voltages with VCC at 3.3 V.
5 2Y3 tri_state Buffered output of bank 2 (from 2A3), in the high-impedance state while 2OE is high.
6 1A3 input Data input to the third buffer of bank 1; active bus-hold holds it at a valid logic level when floating and it accepts 5.5-V input voltages with VCC at 3.3 V.
7 2Y2 tri_state Buffered output of bank 2 (from 2A2), in the high-impedance state while 2OE is high.
8 1A4 input Data input to the fourth buffer of bank 1; active bus-hold holds it at a valid logic level when floating and it accepts 5.5-V input voltages with VCC at 3.3 V.
9 2Y1 tri_state Buffered output of bank 2 (from 2A1), in the high-impedance state while 2OE is high.
10 GND power_in Ground reference for the device.
11 2A1 input Data input to the first buffer of bank 2; active bus-hold holds it at a valid logic level when floating and it accepts 5.5-V input voltages with VCC at 3.3 V.
12 1Y4 tri_state Buffered output of bank 1 (from 1A4), in the high-impedance state while 1OE is high.
13 2A2 input Data input to the second buffer of bank 2; active bus-hold holds it at a valid logic level when floating and it accepts 5.5-V input voltages with VCC at 3.3 V.
14 1Y3 tri_state Buffered output of bank 1 (from 1A3), in the high-impedance state while 1OE is high.
15 2A3 input Data input to the third buffer of bank 2; active bus-hold holds it at a valid logic level when floating and it accepts 5.5-V input voltages with VCC at 3.3 V.
16 1Y2 tri_state Buffered output of bank 1 (from 1A2), in the high-impedance state while 1OE is high.
17 2A4 input Data input to the fourth buffer of bank 2; active bus-hold holds it at a valid logic level when floating and it accepts 5.5-V input voltages with VCC at 3.3 V.
18 1Y1 tri_state Buffered output of bank 1 (from 1A1), in the high-impedance state while 1OE is high.
19 2OE input Active-low output enable for buffers 2Y1 to 2Y4; when low the 2A inputs pass to the 2Y outputs, and when high the outputs are in the high-impedance state.
20 VCC power_in Supply voltage, 2.7 V to 3.6 V recommended operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 4.6 V 3
Input voltage range VI -0.5 7 V see Note 1 3
Output voltage range, high or power-off state VO -0.5 7 V see Note 1 3
Output current, low state IO 128 mA SN74LVTZ244 3
Output current, high state IO 64 mA SN74LVTZ244, see Note 2 3
Input clamp current IIK -50 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Maximum power dissipation, PW package 0.7 W TA = 55°C, still air, see Note 3 3
Operating free-air temperature TA -40 85 °C SN74LVTZ244 3
Storage temperature range Tstg -65 150 °C 3
Supply voltage VCC 2.7 3.6 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
Input voltage VI 5.5 V 3
High-level output current IOH -32 mA 3
Low-level output current IOL 64 mA 3
Input transition rise or fall rate Δt/Δv 10 ns/V Outputs enabled 3
Power-up ramp rate Δt/ΔVCC 200 µs/V 3
Operating free-air temperature TA -40 85 °C 3
Input clamp voltage VIK -1.2 V VCC = 2.7 V, II = −18 mA 4
High-level output voltage VOH -0.2 V VCC = MIN to MAX, IOH = −100 µA (min is VCC−0.2) 4
High-level output voltage VOH 2.4 V VCC = 2.7 V, IOH = −8 mA 4
High-level output voltage VOH 2 V VCC = 3 V, IOH = −32 mA 4
Low-level output voltage VOL 0.2 V VCC = 2.7 V, IOL = 100 µA 4
Low-level output voltage VOL 0.5 V VCC = 2.7 V, IOL = 24 mA 4
Low-level output voltage VOL 0.4 V VCC = 3 V, IOL = 16 mA 4
Low-level output voltage VOL 0.55 V VCC = 3 V, IOL = 64 mA 4
Input current II 10 µA VCC = 0 or MAX, VI = 5.5 V 4
Input current, control inputs II -1 1 µA VCC = 3.6 V, VI = VCC or GND, control inputs 4
Input current, data inputs II 1 µA VCC = 0 to 3.6 V, VI = VCC, data inputs 4
Input current, data inputs II -5 µA VCC = 0 to 3.6 V, VI = 0, data inputs 4
Power-off output current Ioff -100 100 µA VCC = 0 V, VI or VO = 0 to 4.5 V 4
Power-up 3-state output current IOZPU -50 50 µA VCC = 0 V to 1.5 V, VO = 0.5 V to 3 V, OE = X 4
Power-down 3-state output current IOZPD -50 50 µA VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = X 4
Bus-hold current, A inputs II(hold) 75 µA VCC = 3 V, VI = 0.8 V 4
Bus-hold current, A inputs II(hold) -75 µA VCC = 3 V, VI = 2 V 4
Off-state output current, high IOZH 5 µA VCC = 3.6 V, VO = 3 V 4
Off-state output current, low IOZL -5 µA VCC = 3.6 V, VO = 0.5 V 4
Supply current, outputs high ICC 0.12 0.225 mA VCC = 3.6 V, IO = 0, VI = VCC or GND, outputs high 4
Supply current, outputs low ICC 8.6 15 mA VCC = 3.6 V, IO = 0, VI = VCC or GND, outputs low 4
Supply current, outputs disabled ICC 0.12 0.225 mA VCC = 3.6 V, IO = 0, VI = VCC or GND, outputs disabled 4
Supply current change per input ΔICC 0.2 mA VCC = 3 V to 3.6 V, one input at VCC − 0.6 V, other inputs at VCC or GND 4
Input capacitance Ci 4 pF VI = 3 V or 0 4
Output capacitance Co 8 pF VO = 3 V or 0 4
Propagation delay A to Y (low-to-high) tPLH 1 2.5 4.1 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Propagation delay A to Y (low-to-high) tPLH 5 ns VCC = 2.7 V, CL = 50 pF 5
Propagation delay A to Y (high-to-low) tPHL 1 2.5 4.1 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Propagation delay A to Y (high-to-low) tPHL 5.2 ns VCC = 2.7 V, CL = 50 pF 5
Enable time OE to Y (high) tPZH 1 2.7 5.2 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Enable time OE to Y (high) tPZH 6.3 ns VCC = 2.7 V, CL = 50 pF 5
Enable time OE to Y (low) tPZL 1.1 3.1 5.2 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Enable time OE to Y (low) tPZL 6.7 ns VCC = 2.7 V, CL = 50 pF 5
Disable time OE to Y (high) tPHZ 1.9 3.9 5.6 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Disable time OE to Y (high) tPHZ 6.3 ns VCC = 2.7 V, CL = 50 pF 5
Disable time OE to Y (low) tPLZ 1.8 3.2 5.1 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Disable time OE to Y (low) tPLZ 5.6 ns VCC = 2.7 V, CL = 50 pF 5

CAD (KiCad official)

  • Symbol: SN74LVTZ244PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvtz244pwr-etched.step / sn74lvtz244pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvtz244pwr.step / sn74lvtz244pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 e61b13eab83ab019, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF