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SN74LVTH543PWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVTH543PWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-24

SN74LVTH543PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LEBA input B-to-A latch enable: with CEBA low and LEBA low the B-to-A latches are transparent, and a low-to-high transition of LEBA stores the data (datasheet, page 2).
2 OEBA input B-to-A output enable: with CEBA and OEBA both low the A outputs are active, and OE should be tied to VCC through a pullup resistor to keep outputs high-impedance above 1.5 V during power-up/power-down.
3 A1 bidirectional A-port data bit 1 of the octal transceiver; 3-state output that is driven when OEBA and CEBA are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
4 A2 bidirectional A-port data bit 2 of the octal transceiver; 3-state output that is driven when OEBA and CEBA are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
5 A3 bidirectional A-port data bit 3 of the octal transceiver; 3-state output that is driven when OEBA and CEBA are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
6 A4 bidirectional A-port data bit 4 of the octal transceiver; 3-state output that is driven when OEBA and CEBA are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
7 A5 bidirectional A-port data bit 5 of the octal transceiver; 3-state output that is driven when OEBA and CEBA are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
8 A6 bidirectional A-port data bit 6 of the octal transceiver; 3-state output that is driven when OEBA and CEBA are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
9 A7 bidirectional A-port data bit 7 of the octal transceiver; 3-state output that is driven when OEBA and CEBA are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
10 A8 bidirectional A-port data bit 8 of the octal transceiver; 3-state output that is driven when OEBA and CEBA are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
11 CEAB input A-to-B enable: must be low to enter data from A or to output data from B.
12 GND power_in Ground reference for the device.
13 OEAB input A-to-B output enable: with CEAB and OEAB both low the 3-state B outputs are active and reflect the A latch data.
14 LEAB input A-to-B latch enable: with CEAB and LEAB low the A-to-B latches are transparent, and a low-to-high transition of LEAB stores the data.
15 B8 bidirectional B-port data bit 8 of the octal transceiver; 3-state output that is driven when OEAB and CEAB are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
16 B7 bidirectional B-port data bit 7 of the octal transceiver; 3-state output that is driven when OEAB and CEAB are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
17 B6 bidirectional B-port data bit 6 of the octal transceiver; 3-state output that is driven when OEAB and CEAB are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
18 B5 bidirectional B-port data bit 5 of the octal transceiver; 3-state output that is driven when OEAB and CEAB are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
19 B4 bidirectional B-port data bit 4 of the octal transceiver; 3-state output that is driven when OEAB and CEAB are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
20 B3 bidirectional B-port data bit 3 of the octal transceiver; 3-state output that is driven when OEAB and CEAB are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
21 B2 bidirectional B-port data bit 2 of the octal transceiver; 3-state output that is driven when OEAB and CEAB are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
22 B1 bidirectional B-port data bit 1 of the octal transceiver; 3-state output that is driven when OEAB and CEAB are low, with bus-hold on the input and 5-V tolerant inputs with VCC at 3.3 V.
23 CEBA input B-to-A enable: must be low to enter data from B or to output data from A.
24 VCC power_in Supply voltage; recommended operating range is 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Logic
Pins 24

CAD (KiCad official)

  • Symbol: SN74LVTH543PWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: sn74lvth543pwr-etched.step / sn74lvth543pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth543pwr.step / sn74lvth543pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 16482118de43e719, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF