SN74LVT574DWR

{
  "slug": "sn74lvt574dwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "sn74lvt574dwr",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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    "sn74lvt574dwr.step",
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  "component": {
    "mpn": "SN74LVT574DWR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-20-300mil",
    "pin_count": 20,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://www.ti.com/cn/lit/gpn/sn74lvt574",
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      "lbr": "sn74lvt574dwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2862795",
      "digikey": "296-SN74LVT574DWRTR-ND",
      "mouser": "595-SN74LVT574DWR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T16:33:44Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-SN74LVT574DWRTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-SN74LVT574DWR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "OE",
        "type": "input",
        "description": "Buffered active-low output enable: when low the eight 3-state outputs are enabled, when high they go to high impedance, and it does not affect the flip-flop internal operation."
      },
      {
        "number": "2",
        "name": "1D",
        "type": "input",
        "description": "Data input to flip-flop 1, sampled on the positive CLK transition; bus-hold circuitry holds a floating input at a valid level and recommended input voltage is up to 5.5 V."
      },
      {
        "number": "3",
        "name": "2D",
        "type": "input",
        "description": "Data input to flip-flop 2, sampled on the positive CLK transition; bus-hold circuitry holds a floating input at a valid level and recommended input voltage is up to 5.5 V."
      },
      {
        "number": "4",
        "name": "3D",
        "type": "input",
        "description": "Data input to flip-flop 3, sampled on the positive CLK transition; bus-hold circuitry holds a floating input at a valid level and recommended input voltage is up to 5.5 V."
      },
      {
        "number": "5",
        "name": "4D",
        "type": "input",
        "description": "Data input to flip-flop 4, sampled on the positive CLK transition; bus-hold circuitry holds a floating input at a valid level and recommended input voltage is up to 5.5 V."
      },
      {
        "number": "6",
        "name": "5D",
        "type": "input",
        "description": "Data input to flip-flop 5, sampled on the positive CLK transition; bus-hold circuitry holds a floating input at a valid level and recommended input voltage is up to 5.5 V."
      },
      {
        "number": "7",
        "name": "6D",
        "type": "input",
        "description": "Data input to flip-flop 6, sampled on the positive CLK transition; bus-hold circuitry holds a floating input at a valid level and recommended input voltage is up to 5.5 V."
      },
      {
        "number": "8",
        "name": "7D",
        "type": "input",
        "description": "Data input to flip-flop 7, sampled on the positive CLK transition; bus-hold circuitry holds a floating input at a valid level and recommended input voltage is up to 5.5 V."
      },
      {
        "number": "9",
        "name": "8D",
        "type": "input",
        "description": "Data input to flip-flop 8, sampled on the positive CLK transition; bus-hold circuitry holds a floating input at a valid level and recommended input voltage is up to 5.5 V."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "11",
        "name": "CLK",
        "type": "input",
        "description": "Clock input; the Q outputs take the logic levels present on the D inputs on each positive transition, with clock frequency up to 150 MHz."
      },
      {
        "number": "12",
        "name": "8Q",
        "type": "tri_state",
        "description": "Three-state output of flip-flop 8, high impedance when OE is high; IOH is limited to -32 mA and IOL to 64 mA at VCC = 3 V for the SN74LVT574."
      },
      {
        "number": "13",
        "name": "7Q",
        "type": "tri_state",
        "description": "Three-state output of flip-flop 7, high impedance when OE is high; IOH is limited to -32 mA and IOL to 64 mA at VCC = 3 V for the SN74LVT574."
      },
      {
        "number": "14",
        "name": "6Q",
        "type": "tri_state",
        "description": "Three-state output of flip-flop 6, high impedance when OE is high; IOH is limited to -32 mA and IOL to 64 mA at VCC = 3 V for the SN74LVT574."
      },
      {
        "number": "15",
        "name": "5Q",
        "type": "tri_state",
        "description": "Three-state output of flip-flop 5, high impedance when OE is high; IOH is limited to -32 mA and IOL to 64 mA at VCC = 3 V for the SN74LVT574."
      },
      {
        "number": "16",
        "name": "4Q",
        "type": "tri_state",
        "description": "Three-state output of flip-flop 4, high impedance when OE is high; IOH is limited to -32 mA and IOL to 64 mA at VCC = 3 V for the SN74LVT574."
      },
      {
        "number": "17",
        "name": "3Q",
        "type": "tri_state",
        "description": "Three-state output of flip-flop 3, high impedance when OE is high; IOH is limited to -32 mA and IOL to 64 mA at VCC = 3 V for the SN74LVT574."
      },
      {
        "number": "18",
        "name": "2Q",
        "type": "tri_state",
        "description": "Three-state output of flip-flop 2, high impedance when OE is high; IOH is limited to -32 mA and IOL to 64 mA at VCC = 3 V for the SN74LVT574."
      },
      {
        "number": "19",
        "name": "1Q",
        "type": "tri_state",
        "description": "Three-state output of flip-flop 1, high impedance when OE is high; IOH is limited to -32 mA and IOL to 64 mA at VCC = 3 V for the SN74LVT574."
      },
      {
        "number": "20",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply, recommended range 2.7 V to 3.6 V for the SN74LVT574."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The DW (SOIC-20) pinout is not drawn as a separate figure. The pin-to-name mapping comes from the sh; The datasheet's package addendum lists SN74LVT574DWR as SOIC (DW), 20 pins, 2000 per reel, which mat; The schema has no field for headline specs, so none are reported here. For reference, the datasheet "
        ],
        "pages_sent": 18,
        "cost_usd": 0.0813,
        "at": "2026-10-08T16:33:24"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/sn74lvt574",
        "pages": 18,
        "sha256": "5e2b403f93ab6a15",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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}