# SN74LVC573ANSR

**Texas Instruments** · Latches · SOIC-20-208mil

SN74LVC573ANSR from Texas Instruments, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Enable pin for the octal 3-state outputs; the pin-function table gives only the name 'Enable Pin' with no polarity detail in this extract. |
| 2 | 1D | input | Data input 1 of the octal transparent D-type latch. |
| 3 | 2D | input | Data input 2 of the octal transparent D-type latch. |
| 4 | 3D | input | Data input 3 of the octal transparent D-type latch. |
| 5 | 4D | input | Data input 4 of the octal transparent D-type latch. |
| 6 | 5D | input | Data input 5 of the octal transparent D-type latch. |
| 7 | 6D | input | Data input 6 of the octal transparent D-type latch. |
| 8 | 7D | input | Data input 7 of the octal transparent D-type latch. |
| 9 | 8D | input | Data input 8 of the octal transparent D-type latch. |
| 10 | GND | power_in | Ground pin. |
| 11 | LE | input | Latch enable input for the octal transparent D-type latch. |
| 12 | 8Q | tri_state | Output 8 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |
| 13 | 7Q | tri_state | Output 7 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |
| 14 | 6Q | tri_state | Output 6 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |
| 15 | 5Q | tri_state | Output 5 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |
| 16 | 4Q | tri_state | Output 4 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |
| 17 | 3Q | tri_state | Output 3 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |
| 18 | 2Q | tri_state | Output 2 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |
| 19 | 1Q | tri_state | Output 1 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |
| 20 | VCC | power_in | Power pin; the SN74LVC573A operates from 1.65 V to 3.6 V VCC. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-208mil |
| Category | Logic |
| Pins | 20 |

## CAD (KiCad official)

- Symbol: `SN74LVC573ANSR`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-208mil (KiCad packages3D, STEP)
- 3D model files: `sn74lvc573ansr-etched.step` / `sn74lvc573ansr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc573ansr.step` / `sn74lvc573ansr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc573a) (35 pp, sha256 `c42a7e40619c1608`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74lvc573ansr-datasheet.pdf)