component
SN74LVC573ANSR
Public Made by Adomby adom
Texas Instruments Latches, SOIC-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# SN74LVC573ANSR++**Texas Instruments** · Latches · SOIC-20-208mil++SN74LVC573ANSR from Texas Instruments, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Enable pin for the octal 3-state outputs; the pin-function table gives only the name 'Enable Pin' with no polarity detail in this extract. |+| 2 | 1D | input | Data input 1 of the octal transparent D-type latch. |+| 3 | 2D | input | Data input 2 of the octal transparent D-type latch. |+| 4 | 3D | input | Data input 3 of the octal transparent D-type latch. |+| 5 | 4D | input | Data input 4 of the octal transparent D-type latch. |+| 6 | 5D | input | Data input 5 of the octal transparent D-type latch. |+| 7 | 6D | input | Data input 6 of the octal transparent D-type latch. |+| 8 | 7D | input | Data input 7 of the octal transparent D-type latch. |+| 9 | 8D | input | Data input 8 of the octal transparent D-type latch. |+| 10 | GND | power_in | Ground pin. |+| 11 | LE | input | Latch enable input for the octal transparent D-type latch. |+| 12 | 8Q | tri_state | Output 8 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |+| 13 | 7Q | tri_state | Output 7 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |+| 14 | 6Q | tri_state | Output 6 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |+| 15 | 5Q | tri_state | Output 5 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |+| 16 | 4Q | tri_state | Output 4 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |+| 17 | 3Q | tri_state | Output 3 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |+| 18 | 2Q | tri_state | Output 2 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |+| 19 | 1Q | tri_state | Output 1 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. |+| 20 | VCC | power_in | Power pin; the SN74LVC573A operates from 1.65 V to 3.6 V VCC. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-208mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74LVC573ANSR`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-208mil (KiCad packages3D, STEP)+- 3D model files: `sn74lvc573ansr-etched.step` / `sn74lvc573ansr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc573ansr.step` / `sn74lvc573ansr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc573a) (35 pp, sha256 `c42a7e40619c1608`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc573ansr-datasheet.pdf)
page.jsonadded+272@@ -0,0 +1,272 @@+{+ "slug": "sn74lvc573ansr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Latches, SOIC-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lvc573ansr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvc573ansr.kicad_sym",+ "sn74lvc573ansr.kicad_mod",+ "sn74lvc573ansr.glb",+ "sn74lvc573ansr.step",+ "sn74lvc573ansr.lbr",+ "docs/hero.png",+ "docs/sn74lvc573ansr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74lvc573ansr-hero.glb",+ "sn74lvc573ansr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74LVC573ANSR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20-208mil",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74lvc573a",+ "parts": {+ "symbol": "sn74lvc573ansr.kicad_sym",+ "footprint": "sn74lvc573ansr.kicad_mod",+ "model_3d": "sn74lvc573ansr-hero.glb",+ "model_3d_plain": "sn74lvc573ansr.glb",+ "model_3d_step": "sn74lvc573ansr-etched.step",+ "model_3d_step_plain": "sn74lvc573ansr.step",+ "lbr": "sn74lvc573ansr.lbr"+ },+ "distributor_links": {+ "lcsc": "C80329",+ "digikey": "296-29292-2-ND",+ "mouser": "595-SN74LVC573ANSR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T01:05:14Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-29292-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74LVC573ANSR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Enable pin for the octal 3-state outputs; the pin-function table gives only the name 'Enable Pin' with no polarity detail in this extract."+ },+ {+ "number": "2",+ "name": "1D",+ "type": "input",+ "description": "Data input 1 of the octal transparent D-type latch."+ },+ {+ "number": "3",+ "name": "2D",+ "type": "input",+ "description": "Data input 2 of the octal transparent D-type latch."+ },+ {+ "number": "4",+ "name": "3D",+ "type": "input",+ "description": "Data input 3 of the octal transparent D-type latch."+ },+ {+ "number": "5",+ "name": "4D",+ "type": "input",+ "description": "Data input 4 of the octal transparent D-type latch."+ },+ {+ "number": "6",+ "name": "5D",+ "type": "input",+ "description": "Data input 5 of the octal transparent D-type latch."+ },+ {+ "number": "7",+ "name": "6D",+ "type": "input",+ "description": "Data input 6 of the octal transparent D-type latch."+ },+ {+ "number": "8",+ "name": "7D",+ "type": "input",+ "description": "Data input 7 of the octal transparent D-type latch."+ },+ {+ "number": "9",+ "name": "8D",+ "type": "input",+ "description": "Data input 8 of the octal transparent D-type latch."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin."+ },+ {+ "number": "11",+ "name": "LE",+ "type": "input",+ "description": "Latch enable input for the octal transparent D-type latch."+ },+ {+ "number": "12",+ "name": "8Q",+ "type": "tri_state",+ "description": "Output 8 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads."+ },+ {+ "number": "13",+ "name": "7Q",+ "type": "tri_state",+ "description": "Output 7 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads."+ },+ {+ "number": "14",+ "name": "6Q",+ "type": "tri_state",+ "description": "Output 6 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads."+ },+ {+ "number": "15",+ "name": "5Q",+ "type": "tri_state",+ "description": "Output 5 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads."+ },+ {+ "number": "16",+ "name": "4Q",+ "type": "tri_state",+ "description": "Output 4 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads."+ },+ {+ "number": "17",+ "name": "3Q",+ "type": "tri_state",+ "description": "Output 3 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads."+ },+ {+ "number": "18",+ "name": "2Q",+ "type": "tri_state",+ "description": "Output 2 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads."+ },+ {+ "number": "19",+ "name": "1Q",+ "type": "tri_state",+ "description": "Output 1 of the octal latch with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Power pin; the SN74LVC573A operates from 1.65 V to 3.6 V VCC."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package hint says SOIC-20-208mil, but the datasheet's SOIC-20 is the DW package (300 mil, 12.80 x 7.; The pin-function table has merged column headers. The numeric pin column used here is the one that t; The datasheet extract gives no polarity or enable logic for OE and no transparency or latch-timing b"+ ],+ "pages_sent": 9,+ "cost_usd": 0.0675,+ "at": "2026-10-08T01:04:53"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74lvc573a",+ "pages": 35,+ "sha256": "c42a7e40619c1608",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74lvc573ansr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74lvc573ansr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7ac63cfa0f32c4c7bc098dcba87361a152d65a1d1b34a4babacc39b9398ec5d7",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}