component
SN74LVC2G86DCUR
Public Made by Adomby adom
Texas Instruments Gates, VSSOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
sn74lvc2g86dcur: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
91baf8c
20h ago
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{
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"type": "component",
"slug": "sn74lvc2g86dcur",
"title": "SN74LVC2G86DCUR",
"brief": "Texas Instruments Gates, VSSOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.0",
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"manufacturer": "Texas Instruments",
"package": "VSSOP-8",
"pin_count": 8,
"category": "Logic",
"subcategory": "Gates",
"datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc2g86dcur.pdf",
"parts": {
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"footprint": "sn74lvc2g86dcur.kicad_mod",
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"model_3d_plain": "sn74lvc2g86dcur.glb",
"model_3d_step": "sn74lvc2g86dcur-etched.step",
"model_3d_step_plain": "sn74lvc2g86dcur.step",
"lbr": "sn74lvc2g86dcur.lbr"
},
"distributor_links": {
"digikey": "296-13275-2-ND",
"lcsc": "C507252"
},
"pins": [
{
"number": "1",
"name": "1A",
"type": "input",
"description": "Gate 1 input A. CMOS logic input; part of the first XOR gate (Y = A XOR B). VIH/VIL scale with VCC (e.g., VIH = 2 V min at VCC = 3.0-3.6 V). Input voltage tolerated up to 5.5 V regardless of VCC."
},
{
"number": "2",
"name": "1B",
"type": "input",
"description": "Gate 1 input B. CMOS logic input; second input of the first XOR gate. 5.5 V tolerant input; unused inputs must be tied to VCC or GND."
},
{
"number": "3",
"name": "2Y",
"type": "output",
"description": "Gate 2 output. CMOS push-pull output of the second XOR gate (Y = 2A XOR 2B). Drives ±24 mA at VCC = 3.3 V (±32 mA at 4.5 V; ±4 mA at 1.65 V)."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Ground reference (0 V) for the device. Continuous current through GND is limited to ±100 mA."
},
{
"number": "5",
"name": "2A",
"type": "input",
"description": "Gate 2 input A. CMOS logic input; first input of the second XOR gate. 5.5 V tolerant."
},
{
"number": "6",
"name": "2B",
"type": "input",
"description": "Gate 2 input B. CMOS logic input; second input of the second XOR gate. 5.5 V tolerant; tie unused inputs to VCC or GND."
},
{
"number": "7",
"name": "1Y",
"type": "output",
"description": "Gate 1 output. CMOS push-pull output of the first XOR gate (Y = 1A XOR 1B). Drives ±24 mA at VCC = 3.3 V."
},
{
"number": "8",
"name": "VCC",
"type": "power_in",
"description": "Positive supply input. Operating range 1.65 V to 5.5 V (data retention down to 1.5 V). Bypass with a local ceramic capacitor to GND. Absolute maximum 6.5 V."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/sn74lvc2g86dcur.pdf",
"pages": 19,
"sha256": "5e1ba8d249a642f9",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"pin1": {
"pad": "1",
"at": [
-1.4,
-0.75
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "VSSOP-8_2.3x2mm_P0.5mm@sha256:dca72da69de3263a",
"mark": "drawn"
},
"logic": {
"family_id": "74LVC2G86",
"logic_family": "74LVC",
"function_code": "2G86",
"function_class": "Gate",
"function_name": "2-gate variant of Quad 2-Input XOR Gate (86)",
"manufacturer": "Texas Instruments",
"is_specialty": false
},
"models_3d": [
{
"file": "sn74lvc2g86dcur.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
3.1,
2.0,
0.85
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "sn74lvc2g86dcur-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
3.1,
2.0,
0.85
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "6edaea8727dc6342110c597c1baed8dddd2f75b304b537f4f63d5a592e18d77d",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "VSSOP-8",
"Category": "Logic",
"Pins": "8"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"sn74lvc2g86dcur"
],
"discovery_pitch": "SN74LVC2G86DCUR (Texas Instruments) component page with datasheet-verified CAD.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"sn74lvc2g86dcur.kicad_sym",
"sn74lvc2g86dcur.kicad_mod",
"sn74lvc2g86dcur.glb",
"sn74lvc2g86dcur.step",
"sn74lvc2g86dcur-etched.step",
"sn74lvc2g86dcur.lbr",
"docs/hero.png",
"docs/sn74lvc2g86dcur-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"variants": [
{
"mpn": "SN74LVC2G86DCUR",
"kind": "packaging"
},
{
"mpn": "SN74LVC2G86DCURG4",
"kind": "packaging"
},
{
"mpn": "SN74LVC2G86DCURDCUT",
"kind": "packaging"
},
{
"mpn": "SN74LVC2G86DCURDCTR",
"kind": "packaging"
},
{
"mpn": "SN74LVC2G86DCURYZPR",
"kind": "packaging"
}
],
"updated_at": "2026-09-25T07:46:10.931Z"
}