SN74LVC2G86DCUR

{
 "schema": "adom.pads/1",
 "slug": "sn74lvc2g86dcur",
 "footprint": "VSSOP-8_2.3x2mm_P0.5mm",
 "generated_from": {
  "footprint": "VSSOP-8_2.3x2mm_P0.5mm@sha256:dca72da69de3263a",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -1.4,
   -0.75
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "VSSOP-8_2.3x2mm_P0.5mm@sha256:dca72da69de3263a"
 },
 "pad_count": 8,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5",
  "6",
  "7",
  "8"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.4,
    -0.75
   ],
   "rot": 0.0,
   "size": [
    1.25,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "1A",
   "type": "input",
   "description": "Gate 1 input A. CMOS logic input; part of the first XOR gate (Y = A XOR B). VIH/VIL scale with VCC (e.g., VIH = 2 V min at VCC = 3.0-3.6 V). Input voltage tolerated up to 5.5 V regardless of VCC.",
   "is_pin1": true,
   "source": {
    "geometry": "VSSOP-8_2.3x2mm_P0.5mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.4,
    -0.25
   ],
   "rot": 0.0,
   "size": [
    1.25,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "1B",
   "type": "input",
   "description": "Gate 1 input B. CMOS logic input; second input of the first XOR gate. 5.5 V tolerant input; unused inputs must be tied to VCC or GND.",
   "is_pin1": false,
   "source": {
    "geometry": "VSSOP-8_2.3x2mm_P0.5mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.4,
    0.25
   ],
   "rot": 0.0,
   "size": [
    1.25,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "2Y",
   "type": "output",
   "description": "Gate 2 output. CMOS push-pull output of the second XOR gate (Y = 2A XOR 2B). Drives ±24 mA at VCC = 3.3 V (±32 mA at 4.5 V; ±4 mA at 1.65 V).",
   "is_pin1": false,
   "source": {
    "geometry": "VSSOP-8_2.3x2mm_P0.5mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.4,
    0.75
   ],
   "rot": 0.0,
   "size": [
    1.25,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference (0 V) for the device. Continuous current through GND is limited to ±100 mA.",
   "is_pin1": false,
   "source": {
    "geometry": "VSSOP-8_2.3x2mm_P0.5mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.4,
    0.75
   ],
   "rot": 0.0,
   "size": [
    1.25,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "2A",
   "type": "input",
   "description": "Gate 2 input A. CMOS logic input; first input of the second XOR gate. 5.5 V tolerant.",
   "is_pin1": false,
   "source": {
    "geometry": "VSSOP-8_2.3x2mm_P0.5mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "6",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.4,
    0.25
   ],
   "rot": 0.0,
   "size": [
    1.25,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "6",
   "name": "2B",
   "type": "input",
   "description": "Gate 2 input B. CMOS logic input; second input of the second XOR gate. 5.5 V tolerant; tie unused inputs to VCC or GND.",
   "is_pin1": false,
   "source": {
    "geometry": "VSSOP-8_2.3x2mm_P0.5mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "7",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.4,
    -0.25
   ],
   "rot": 0.0,
   "size": [
    1.25,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "7",
   "name": "1Y",
   "type": "output",
   "description": "Gate 1 output. CMOS push-pull output of the first XOR gate (Y = 1A XOR 1B). Drives ±24 mA at VCC = 3.3 V.",
   "is_pin1": false,
   "source": {
    "geometry": "VSSOP-8_2.3x2mm_P0.5mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "8",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.4,
    -0.75
   ],
   "rot": 0.0,
   "size": [
    1.25,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "8",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply input. Operating range 1.65 V to 5.5 V (data retention down to 1.5 V). Bypass with a local ceramic capacitor to GND. Absolute maximum 6.5 V.",
   "is_pin1": false,
   "source": {
    "geometry": "VSSOP-8_2.3x2mm_P0.5mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}