main
Ray
sn74lvc1g08: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
757da05
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221
{
"schema_version": 1,
"type": "component",
"slug": "sn74lvc1g08",
"title": "SN74LVC1G08 Single AND Gate",
"brief": "Single 2-input AND gate",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"logic",
"single-gate",
"lvc",
"cmos",
"ti",
"sot-23-5"
],
"component": {
"mpn": "SN74LVC1G08",
"manufacturer": "Texas Instruments",
"package": "SOT-23-5",
"pin_count": 5,
"category": "Logic",
"subcategory": "Logic Gate",
"datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc1g08.pdf",
"parts": {
"symbol": "sn74lvc1g08.kicad_sym",
"footprint": "sn74lvc1g08.kicad_mod",
"model_3d": "sn74lvc1g08-etched.glb",
"model_3d_plain": "sn74lvc1g08.glb",
"model_3d_step": "sn74lvc1g08-etched.step",
"model_3d_step_plain": "sn74lvc1g08.step",
"lbr": "sn74lvc1g08.lbr"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "A",
"type": "input",
"description": "Logic input A of the 2-input AND gate. Standard CMOS input, high impedance; VIH = 0.65×VCC (at VCC=1.65-1.95V) to 0.7×VCC (at 4.5-5.5V). Input voltage tolerant up to 5.5V regardless of VCC."
},
{
"number": "2",
"name": "B",
"type": "input",
"description": "Logic input B of the 2-input AND gate. Standard CMOS input, high impedance, 5.5V-tolerant. Must not be left floating; terminate unused inputs at VCC or GND."
},
{
"number": "3",
"name": "GND",
"type": "power_in",
"description": "Ground reference (0V). Continuous current through GND rated ±100mA max."
},
{
"number": "4",
"name": "Y",
"type": "output",
"description": "AND-gate output Y = A · B. Balanced CMOS push-pull; ±24mA drive at VCC=3V (±32mA at 4.5V). Do not connect unused push-pull outputs."
},
{
"number": "5",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage. Operating range 1.65V to 5.5V; data retention only down to 1.5V. Absolute max 6.5V. ICC = 10µA max."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/sn74lvc1g08.pdf",
"pages": 50,
"sha256": "de1b842781b3078f",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 5,
"described": 5,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"logic": {
"family_id": "74LVC1G08",
"logic_family": "74LVC",
"function_code": "1G08",
"function_class": "Gate",
"function_name": "1-gate variant of Quad 2-Input AND Gate (08)",
"manufacturer": "Texas Instruments",
"is_specialty": false
},
"models_3d": [
{
"file": "sn74lvc1g08.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
2.8,
2.9,
1.55
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "720a6eab0024069bbee68e7cb4c3ff1149468a34611225cdc852662c5d0ec2b7",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "sn74lvc1g08-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
2.8,
2.9,
1.55
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "6cdb3e469df0354392a78da112f97bd8177d7acb0a1f7567161147e471631f6e",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Type": "Single 2-input AND gate",
"Logic family": "LVC (CMOS)",
"Supply voltage": "1.65 V to 5.5 V",
"Input tolerance": "5 V tolerant",
"Propagation delay": "3.5 ns typ at 3.3 V",
"Operating temperature": "-40 C to 125 C"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"single gate",
"one-gate logic",
"glue logic",
"board-edge logic"
],
"discovery_pitch": "One 2-input AND gate in a 5-pin package for glue logic exactly where you need it.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"sn74lvc1g08.kicad_sym",
"sn74lvc1g08.kicad_mod",
"sn74lvc1g08.glb",
"sn74lvc1g08.step",
"sn74lvc1g08.lbr",
"docs/hero.png",
"docs/sn74lvc1g08-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"sn74lvc1g08-etched.step"
],
"variants": [
{
"mpn": "SN74LVC1G08DBVR",
"kind": "unknown"
},
{
"mpn": "SN74LVC1G08DBVT",
"kind": "unknown"
},
{
"mpn": "SN74LVC1G08DCKR",
"kind": "unknown"
},
{
"mpn": "SN74LVC1G08DCKT",
"kind": "unknown"
},
{
"mpn": "SN74LVC1G08DRLR",
"kind": "unknown"
},
{
"mpn": "SN74LVC1G08YZPR",
"kind": "unknown"
},
{
"mpn": "SN74LVC1G08DRYR",
"kind": "unknown"
},
{
"mpn": "SN74LVC1G08DSFR",
"kind": "unknown"
},
{
"mpn": "SN74LVC1G08DPWR",
"kind": "unknown"
}
]
}