SN74LVC1G00DCKR

{
 "schema": "adom.pads/1",
 "slug": "sn74lvc1g00dckr",
 "footprint": "SOT-353_SC-70-5",
 "generated_from": {
  "footprint": "SOT-353_SC-70-5@sha256:869e17094994ff78",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -0.8375,
   -0.65
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOT-353_SC-70-5@sha256:869e17094994ff78"
 },
 "pad_count": 5,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "A",
   "type": "input",
   "description": "Logic input A of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); high-level threshold is 0.65×VCC to 0.7×VCC depending on VCC rail.",
   "is_pin1": true,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "B",
   "type": "input",
   "description": "Logic input B of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); shares the same input thresholds as pin A.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference (0V) for the device. Continuous current through GND is rated ±100mA maximum.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "Y",
   "type": "output",
   "description": "NAND gate output, Y = NOT(A AND B). Drives ±24mA at VCC = 3V and up to ±32mA at VCC = 4.5V; features Ioff partial-power-down and back-drive protection.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply voltage. Operating range is 1.65V to 5.5V (1.5V minimum for data retention); ICC is typically <10µA. Bypass with a local decoupling capacitor.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}