component
SN74LVC1G00DCKR
Public Made by Adomby adom
UMW Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
5 files changed
+316−122
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/sn74lvc1g00dckr-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+182@@ -0,0 +1,182 @@+{+ "schema": "adom.pads/1",+ "slug": "sn74lvc1g00dckr",+ "footprint": "SOT-353_SC-70-5",+ "generated_from": {+ "footprint": "SOT-353_SC-70-5@sha256:869e17094994ff78",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -0.8375,+ -0.65+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOT-353_SC-70-5@sha256:869e17094994ff78"+ },+ "pad_count": 5,+ "symbol_pins": [+ "1",+ "2",+ "3",+ "4",+ "5"+ ],+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -0.8375,+ -0.65+ ],+ "rot": 0.0,+ "size": [+ 1.025,+ 0.35+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "A",+ "type": "input",+ "description": "Logic input A of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); high-level threshold is 0.65×VCC to 0.7×VCC depending on VCC rail.",+ "is_pin1": true,+ "source": {+ "geometry": "SOT-353_SC-70-5.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -0.8375,+ 0.0+ ],+ "rot": 0.0,+ "size": [+ 1.025,+ 0.35+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "B",+ "type": "input",+ "description": "Logic input B of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); shares the same input thresholds as pin A.",+ "is_pin1": false,+ "source": {+ "geometry": "SOT-353_SC-70-5.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -0.8375,+ 0.65+ ],+ "rot": 0.0,+ "size": [+ 1.025,+ 0.35+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0V) for the device. Continuous current through GND is rated ±100mA maximum.",+ "is_pin1": false,+ "source": {+ "geometry": "SOT-353_SC-70-5.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 0.8375,+ 0.65+ ],+ "rot": 0.0,+ "size": [+ 1.025,+ 0.35+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "Y",+ "type": "output",+ "description": "NAND gate output, Y = NOT(A AND B). Drives ±24mA at VCC = 3V and up to ±32mA at VCC = 4.5V; features Ioff partial-power-down and back-drive protection.",+ "is_pin1": false,+ "source": {+ "geometry": "SOT-353_SC-70-5.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 0.8375,+ -0.65+ ],+ "rot": 0.0,+ "size": [+ 1.025,+ 0.35+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range is 1.65V to 5.5V (1.5V minimum for data retention); ICC is typically <10µA. Bypass with a local decoupling capacitor.",+ "is_pin1": false,+ "source": {+ "geometry": "SOT-353_SC-70-5.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}
page.json+130−119@@ -1,124 +1,135 @@ {- "schema_version": 1,- "type": "component",- "slug": "sn74lvc1g00dckr",- "title": "SN74LVC1G00DCKR",- "brief": "UMW Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",- "license": "CC-BY-SA-4.0",- "tags": [- "component",- "logic",- "sn74lvc1g00dckr"- ],- "component": {- "mpn": "SN74LVC1G00DCKR",- "manufacturer": "UMW",- "package": "SC-70-5",- "pin_count": 5,- "category": "Logic",- "subcategory": "Gates",- "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf",- "parts": {- "symbol": "sn74lvc1g00dckr.kicad_sym",- "footprint": "sn74lvc1g00dckr.kicad_mod",- "model_3d": "sn74lvc1g00dckr.glb",- "model_3d_step": "sn74lvc1g00dckr.step",- "lbr": "sn74lvc1g00dckr.lbr"+ "schema_version": 1,+ "type": "component",+ "slug": "sn74lvc1g00dckr",+ "title": "SN74LVC1G00DCKR",+ "brief": "UMW Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "version": "0.1.0",+ "license": "CC-BY-SA-4.0",+ "tags": [+ "component",+ "logic",+ "sn74lvc1g00dckr"+ ],+ "component": {+ "mpn": "SN74LVC1G00DCKR",+ "manufacturer": "UMW",+ "package": "SC-70-5",+ "pin_count": 5,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf",+ "parts": {+ "symbol": "sn74lvc1g00dckr.kicad_sym",+ "footprint": "sn74lvc1g00dckr.kicad_mod",+ "model_3d": "sn74lvc1g00dckr.glb",+ "model_3d_step": "sn74lvc1g00dckr.step",+ "lbr": "sn74lvc1g00dckr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Logic input A of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); high-level threshold is 0.65×VCC to 0.7×VCC depending on VCC rail."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Logic input B of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); shares the same input thresholds as pin A."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0V) for the device. Continuous current through GND is rated ±100mA maximum."+ },+ {+ "number": "4",+ "name": "Y",+ "type": "output",+ "description": "NAND gate output, Y = NOT(A AND B). Drives ±24mA at VCC = 3V and up to ±32mA at VCC = 4.5V; features Ioff partial-power-down and back-drive protection."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range is 1.65V to 5.5V (1.5V minimum for data retention); ICC is typically <10µA. Bypass with a local decoupling capacitor."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf",+ "pages": 50,+ "sha256": "1264f79853e6119b",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 5,+ "described": 5,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "pin1": {+ "pad": "1",+ "at": [+ -0.8375,+ -0.65+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOT-353_SC-70-5@sha256:869e17094994ff78",+ "mark": "drawn"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Unknown",+ "Package": "SC-70-5",+ "Category": "Logic",+ "Pins": "5"+ } },- "distributor_links": {},- "pins": [- {- "number": "1",- "name": "A",- "type": "input",- "description": "Logic input A of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); high-level threshold is 0.65\u00d7VCC to 0.7\u00d7VCC depending on VCC rail."- },- {- "number": "2",- "name": "B",- "type": "input",- "description": "Logic input B of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); shares the same input thresholds as pin A."- },- {- "number": "3",- "name": "GND",- "type": "power_in",- "description": "Ground reference (0V) for the device. Continuous current through GND is rated \u00b1100mA maximum."- },- {- "number": "4",- "name": "Y",- "type": "output",- "description": "NAND gate output, Y = NOT(A AND B). Drives \u00b124mA at VCC = 3V and up to \u00b132mA at VCC = 4.5V; features Ioff partial-power-down and back-drive protection."- },- {- "number": "5",- "name": "VCC",- "type": "power_in",- "description": "Positive supply voltage. Operating range is 1.65V to 5.5V (1.5V minimum for data retention); ICC is typically <10\u00b5A. Bypass with a local decoupling capacitor."- }+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info" ],- "provenance": {- "extractor": "ds2sf",- "datasheet": {- "url": "https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf",- "pages": 50,- "sha256": "1264f79853e6119b",- "source_tier": "mfr"- },- "cad": "KiCad official (CC-BY-SA 4.0)",- "pins": {- "total": 5,- "described": 5,- "cites_pages": true,- "refuses_to_fabricate": true- }+ "discovery_triggers": [+ "sn74lvc1g00dckr"+ ],+ "discovery_pitch": "SN74LVC1G00DCKR (Unknown) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ },+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png" },- "viewers": {- "symbol": "viewers/symbol.html",- "footprint": "viewers/footprint.html"- }- },- "metadata": {- "specs": {- "Manufacturer": "Unknown",- "Package": "SC-70-5",- "Category": "Logic",- "Pins": "5"- }- },- "sections": [- "hero",- "viewers",- "readme",- "breadcrumbs",- "info"- ],- "discovery_triggers": [- "sn74lvc1g00dckr"- ],- "discovery_pitch": "SN74LVC1G00DCKR (Unknown) component page with datasheet-verified CAD.",- "author": {- "name": "Ray",- "email": "[email protected]"- },- "dependencies": {},- "hero": {- "type": "image",- "path": "docs/hero.png"- },- "files": [- "page.json",- "README.md",- "sn74lvc1g00dckr.kicad_sym",- "sn74lvc1g00dckr.kicad_mod",- "sn74lvc1g00dckr.glb",- "sn74lvc1g00dckr.step",- "sn74lvc1g00dckr.lbr",- "docs/hero.png",- "docs/sn74lvc1g00dckr-datasheet.pdf",- "viewers/symbol.html",- "viewers/footprint.html"- ]+ "files": [+ "page.json",+ "README.md",+ "sn74lvc1g00dckr.kicad_sym",+ "sn74lvc1g00dckr.kicad_mod",+ "sn74lvc1g00dckr.glb",+ "sn74lvc1g00dckr.step",+ "sn74lvc1g00dckr.lbr",+ "docs/hero.png",+ "docs/sn74lvc1g00dckr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ] }
sn74lvc1g00dckr.lbr+1−1@@ -68,7 +68,7 @@ <wire x1="0.7350" y1="-1.1100" x2="-0.7350" y2="-1.1100" width="0.1200" layer="21"/> <text x="0" y="1.763" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-1.763" size="1.27" layer="27" align="top-center">>VALUE</text>-</package>+<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.1800" y="1.0900"/><vertex x="-1.3200" y="1.2800"/><vertex x="-1.0400" y="1.2800"/></polygon></package> </packages> <symbols> <symbol name="SN74LVC1G00DCKR">
viewers/footprint.html+1−1@@ -23,7 +23,7 @@ rect.pad.hi{stroke:var(--hi);stroke-width:.15;paint-order:stroke} #tip .td{font-size:11px;color:var(--ink);margin-top:5px;line-height:1.4} </style></head><body> <div class=bar><span class=h>PCB footprint</span><span class=sp></span><button class="lyrtog on" data-lyr="copper"><span class="d" style="background:#e35d5d"></span>Copper</button><button class="lyrtog on" data-lyr="silk"><span class="d" style="background:#e6edf3"></span>Silkscreen</button><button class="lyrtog" data-lyr="fab"><span class="d" style="background:#8b949e"></span>Fab</button><button class="lyrtog" data-lyr="courtyard"><span class="d" style="background:#bc8cff"></span>Courtyard</button></div>-<div class=stage id=stage><svg xmlns='http://www.w3.org/2000/svg' viewBox='-1.850 -1.510 3.700 3.020' style='width:100%;height:100%'><line class='ly-silk' x1='-0.735' y1='-1.110' x2='0.735' y2='-1.110' stroke='#d8b4fe' stroke-width='0.120'/><line class='ly-silk' x1='-0.735' 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