component
SN74LVC1G00DCKR
Public Made by Adomby adom
UMW Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
sn74lvc1g00dckr: manufacturer provenance fix
2 files changed
+122−125
README.md+4−4@@ -1,8 +1,8 @@ # SN74LVC1G00DCKR -**Unknown** · Gates · SC-70-5+**UMW** · Gates · SC-70-5 -SN74LVC1G00DCKR from Unknown, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.+SN74LVC1G00DCKR from UMW, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD. ## Pinout @@ -18,7 +18,7 @@ SN74LVC1G00DCKR from Unknown, in a SC-70-5. Pinout and pin descriptions extracte | Parameter | Value | |---|---|-| Manufacturer | Unknown |+| Manufacturer | UMW | | Package | SC-70-5 | | Category | Logic | | Pins | 5 |@@ -45,7 +45,7 @@ SN74LVC1G00DCKR from Unknown, in a SC-70-5. Pinout and pin descriptions extracte Data extracted from the manufacturer datasheet, not a distributor listing: -- **Datasheet:** [Unknown datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf) (50 pp, sha256 `1264f79853e6119b`, retrieved 2026-08-17, tier: manufacturer)+- **Datasheet:** [UMW datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf) (50 pp, sha256 `1264f79853e6119b`, retrieved 2026-08-17, tier: manufacturer) - **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - **CAD:** KiCad official libraries (CC-BY-SA 4.0).
page.json+118−121@@ -1,127 +1,124 @@ {- "schema_version": 1,- "type": "component",- "slug": "sn74lvc1g00dckr",- "title": "SN74LVC1G00DCKR",- "brief": "Unknown Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",- "license": "CC-BY-SA-4.0",- "tags": [- "component",- "logic",- "sn74lvc1g00dckr"- ],- "component": {- "mpn": "SN74LVC1G00DCKR",- "manufacturer": "Unknown",- "package": "SC-70-5",- "pin_count": 5,- "category": "Logic",- "subcategory": "Gates",- "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf",- "parts": {- "symbol": "sn74lvc1g00dckr.kicad_sym",- "footprint": "sn74lvc1g00dckr.kicad_mod",- "model_3d": "sn74lvc1g00dckr.glb",- "model_3d_step": "sn74lvc1g00dckr.step",- "lbr": "sn74lvc1g00dckr.lbr"- },- "distributor_links": {},- "pins": [- {- "number": "1",- "name": "A",- "type": "input",- "description": "Logic input A of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); high-level threshold is 0.65×VCC to 0.7×VCC depending on VCC rail."- },- {- "number": "2",- "name": "B",- "type": "input",- "description": "Logic input B of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); shares the same input thresholds as pin A."- },- {- "number": "3",- "name": "GND",- "type": "power_in",- "description": "Ground reference (0V) for the device. Continuous current through GND is rated ±100mA maximum."- },- {- "number": "4",- "name": "Y",- "type": "output",- "description": "NAND gate output, Y = NOT(A AND B). Drives ±24mA at VCC = 3V and up to ±32mA at VCC = 4.5V; features Ioff partial-power-down and back-drive protection."- },- {- "number": "5",- "name": "VCC",- "type": "power_in",- "description": "Positive supply voltage. Operating range is 1.65V to 5.5V (1.5V minimum for data retention); ICC is typically <10µA. Bypass with a local decoupling capacitor."- }- ],- "provenance": {- "extractor": "ds2sf",- "datasheet": {- "url": "https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf",- "pages": 50,- "sha256": "1264f79853e6119b",- "source_tier": "mfr"- },- "cad": "KiCad official (CC-BY-SA 4.0)",- "pins": {- "total": 5,- "described": 5,- "cites_pages": true,- "refuses_to_fabricate": true- }- },- "viewers": {- "symbol": "viewers/symbol.html",- "footprint": "viewers/footprint.html"- }- },- "metadata": {- "specs": {- "Manufacturer": "Unknown",- "Package": "SC-70-5",- "Category": "Logic",- "Pins": "5"- }+ "schema_version": 1,+ "type": "component",+ "slug": "sn74lvc1g00dckr",+ "title": "SN74LVC1G00DCKR",+ "brief": "UMW Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "version": "0.1.0",+ "license": "CC-BY-SA-4.0",+ "tags": [+ "component",+ "logic",+ "sn74lvc1g00dckr"+ ],+ "component": {+ "mpn": "SN74LVC1G00DCKR",+ "manufacturer": "UMW",+ "package": "SC-70-5",+ "pin_count": 5,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf",+ "parts": {+ "symbol": "sn74lvc1g00dckr.kicad_sym",+ "footprint": "sn74lvc1g00dckr.kicad_mod",+ "model_3d": "sn74lvc1g00dckr.glb",+ "model_3d_step": "sn74lvc1g00dckr.step",+ "lbr": "sn74lvc1g00dckr.lbr" },- "sections": [- "hero",- "viewers",- "readme",- "breadcrumbs",- "info"- ],- "discovery_triggers": [- "sn74lvc1g00dckr"+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Logic input A of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); high-level threshold is 0.65\u00d7VCC to 0.7\u00d7VCC depending on VCC rail."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Logic input B of the 2-input NAND gate. Accepts input voltages from 0V up to 5.5V regardless of VCC (5V-tolerant); shares the same input thresholds as pin A."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0V) for the device. Continuous current through GND is rated \u00b1100mA maximum."+ },+ {+ "number": "4",+ "name": "Y",+ "type": "output",+ "description": "NAND gate output, Y = NOT(A AND B). Drives \u00b124mA at VCC = 3V and up to \u00b132mA at VCC = 4.5V; features Ioff partial-power-down and back-drive protection."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range is 1.65V to 5.5V (1.5V minimum for data retention); ICC is typically <10\u00b5A. Bypass with a local decoupling capacitor."+ } ],- "discovery_pitch": "SN74LVC1G00DCKR (Unknown) component page with datasheet-verified CAD.",- "author": {- "name": "Ray",- "email": "[email protected]"+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lvc1g00.pdf",+ "pages": 50,+ "sha256": "1264f79853e6119b",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 5,+ "described": 5,+ "cites_pages": true,+ "refuses_to_fabricate": true+ } },- "dependencies": {},- "hero": {- "type": "image",- "path": "docs/hero.png"- },- "files": [- "page.json",- "README.md",- "sn74lvc1g00dckr.kicad_sym",- "sn74lvc1g00dckr.kicad_mod",- "sn74lvc1g00dckr.glb",- "sn74lvc1g00dckr.step",- "sn74lvc1g00dckr.lbr",- "docs/hero.png",- "docs/sn74lvc1g00dckr-datasheet.pdf",- "viewers/symbol.html",- "viewers/footprint.html"- ],- "visibility": {- "public": true+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Unknown",+ "Package": "SC-70-5",+ "Category": "Logic",+ "Pins": "5" }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74lvc1g00dckr"+ ],+ "discovery_pitch": "SN74LVC1G00DCKR (Unknown) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ },+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvc1g00dckr.kicad_sym",+ "sn74lvc1g00dckr.kicad_mod",+ "sn74lvc1g00dckr.glb",+ "sn74lvc1g00dckr.step",+ "sn74lvc1g00dckr.lbr",+ "docs/hero.png",+ "docs/sn74lvc1g00dckr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ] }