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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74LS74ANSR

Texas Instruments · Flip Flops · SOP-14-208mil

SN74LS74ANSR from Texas Instruments, in a SOP-14-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	~1CLR	input	Active-low asynchronous clear input for flip-flop 1; when LOW, forces 1Q LOW and ~1Q HIGH independent of clock, data, or preset; IIH max 20 µA, IIL max −0.4 mA.
2	1D	input	Data input for flip-flop 1; logic state is transferred to 1Q on the positive edge of 1CLK when ~1PRE and ~1CLR are HIGH; IIH max 20 µA, IIL max −0.4 mA.
3	1CLK	input	Positive-edge-triggered clock input for flip-flop 1; maximum clock frequency 25 MHz; setup time before CLK↑ 20 ns, hold time after CLK↑ 5 ns.
4	~1PRE	input	Active-low asynchronous preset input for flip-flop 1; when LOW, forces 1Q HIGH and ~1Q LOW independent of clock or data; IIH max 20 µA, IIL max −0.8 mA.
5	1Q	output	Q output of flip-flop 1; VOH min 2.4 V (IOH = −0.4 mA), VOL max 0.4 V (IOL = 4 mA), IOH max −0.4 mA, IOL max 4 mA.
6	~1Q	output	Complement Q̄ output of flip-flop 1; always the logical inverse of 1Q; VOH min 2.4 V, VOL max 0.4 V under same load conditions as 1Q.
7	GND	power_in	Ground reference (0 V) for all internal logic; all voltages measured with respect to this terminal.
8	~2Q	output	Complement Q̄ output of flip-flop 2; always the logical inverse of 2Q; VOH min 2.4 V, VOL max 0.4 V under same load conditions as 2Q.
9	2Q	output	Q output of flip-flop 2; VOH min 2.4 V (IOH = −0.4 mA), VOL max 0.4 V (IOL = 4 mA).
10	~2PRE	input	Active-low asynchronous preset input for flip-flop 2; when LOW, forces 2Q HIGH and ~2Q LOW independent of clock or data; IIH max 20 µA, IIL max −0.8 mA.
11	2CLK	input	Positive-edge-triggered clock input for flip-flop 2; maximum clock frequency 25 MHz; setup time before CLK↑ 20 ns, hold time after CLK↑ 5 ns.
12	2D	input	Data input for flip-flop 2; logic state is transferred to 2Q on the positive edge of 2CLK when ~2PRE and ~2CLR are HIGH; IIH max 20 µA, IIL max −0.4 mA.
13	~2CLR	input	Active-low asynchronous clear input for flip-flop 2; when LOW, forces 2Q LOW and ~2Q HIGH independent of clock, data, or preset; IIH max 20 µA, IIL max −0.4 mA.
14	VCC	power_in	Positive supply voltage; recommended operating range 4.5 V min to 5.25 V max for SN74LS74A; absolute maximum 7 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOP-14-208mil
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: SN74LS74ANSR
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOP-14-208mil (KiCad packages3D, STEP)
3D model files: sn74ls74ansr-etched.step / sn74ls74ansr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls74ansr.step / sn74ls74ansr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (30 pp, sha256 3c67c755a4225573, retrieved 2026-09-26, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF