component
SN74LS73ADR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74LS73ADR
Texas Instruments · Flip Flops · SOIC-14
SN74LS73ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLK | input | Clock input for flip-flop 1; negative-edge triggered, with J and K stable one setup time before the high-to-low transition. |
| 2 | 1CLR | input | Active-low direct clear for flip-flop 1; when low it overrides clock and data, forcing 1Q low and 1Q̅ high. |
| 3 | 1K | input | K data input for flip-flop 1. |
| 4 | VCC | power_in | Positive supply voltage. |
| 5 | 2CLK | input | Clock input for flip-flop 2; negative-edge triggered, with J and K stable one setup time before the high-to-low transition. |
| 6 | 2CLR | input | Active-low direct clear for flip-flop 2; when low it overrides clock and data, forcing 2Q low and 2Q̅ high. |
| 7 | 2J | input | J data input for flip-flop 2. |
| 8 | 2Q̅ | output | Complementary output of flip-flop 2. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2K | input | K data input for flip-flop 2. |
| 11 | GND | power_in | Ground. |
| 12 | 1Q | output | True output of flip-flop 1. |
| 13 | 1Q̅ | output | Complementary output of flip-flop 1. |
| 14 | 1J | input | J data input for flip-flop 1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LS73ADR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls73adr-etched.step/sn74ls73adr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls73adr.step/sn74ls73adr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
4600f8ed8f5aaf96, retrieved 2026-10-07, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LS73ADR
**Texas Instruments** · Flip Flops · SOIC-14
SN74LS73ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLK | input | Clock input for flip-flop 1; negative-edge triggered, with J and K stable one setup time before the high-to-low transition. |
| 2 | 1CLR | input | Active-low direct clear for flip-flop 1; when low it overrides clock and data, forcing 1Q low and 1Q̅ high. |
| 3 | 1K | input | K data input for flip-flop 1. |
| 4 | VCC | power_in | Positive supply voltage. |
| 5 | 2CLK | input | Clock input for flip-flop 2; negative-edge triggered, with J and K stable one setup time before the high-to-low transition. |
| 6 | 2CLR | input | Active-low direct clear for flip-flop 2; when low it overrides clock and data, forcing 2Q low and 2Q̅ high. |
| 7 | 2J | input | J data input for flip-flop 2. |
| 8 | 2Q̅ | output | Complementary output of flip-flop 2. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2K | input | K data input for flip-flop 2. |
| 11 | GND | power_in | Ground. |
| 12 | 1Q | output | True output of flip-flop 1. |
| 13 | 1Q̅ | output | Complementary output of flip-flop 1. |
| 14 | 1J | input | J data input for flip-flop 1. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `SN74LS73ADR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `sn74ls73adr-etched.step` / `sn74ls73adr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls73adr.step` / `sn74ls73adr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ls73a.pdf) (20 pp, sha256 `4600f8ed8f5aaf96`, retrieved 2026-10-07, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ls73adr-datasheet.pdf)